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1. 发明授权

US08106692B2 Method for tracking delay locked loop clock 有权
标题翻译：跟踪延迟锁定环时钟的方法
公开(公告)号：US08106692B2
公开(公告)日：2012-01-31
申请号：US12717104
申请日：2010-03-03
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： H03L7/06
CPC分类号： H03L7/06
摘要： A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%.
摘要翻译：描述了用于跟踪延迟锁定环（DLL）时钟的方法。在外部时钟信号的第一周期期间，当发生施加在DLL上的轨道信号的过渡沿时，外部时钟信号被允许通过DLL的延迟单元。然后，当在外部时钟信号的第二周期开始时发生施加在DLL上的感测信号的过渡沿时，外部时钟信号被禁止通过延迟单元和延迟单元的数量，对外部时钟信号的第一个周期内的外部信号通过计数。当复位信号被确认时，每个延迟单元的延迟时间被复位，使得延迟时间与外部时钟信号周期的比率保持在10％至15％。

2. 发明申请

US20120001606A1 Voltage regulator circuit 有权
标题翻译：稳压电路
公开(公告)号：US20120001606A1
公开(公告)日：2012-01-05
申请号：US12801917
申请日：2010-07-01
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： G05F1/10
CPC分类号： G11C5/141
摘要： A voltage regulator circuit comprises active and standby amplifiers, first and second transistors, and a capacitor. The active amplifier has a negative input connected to a first reference voltage, and the standby amplifier has a negative input connected to a second reference voltage. The first reference voltage is greater than the second reference voltage. The first transistor has a gate connected to an output of the active amplifier and a drain connected to a voltage regulated output, and the second transistor has a gate connected to an output of the standby amplifier and a drain connected to the voltage regulated output. The capacitor is connected between a chip enable signal and the voltage regulated output.
摘要翻译：电压调节器电路包括有源和备用放大器，第一和第二晶体管以及电容器。有源放大器具有连接到第一参考电压的负输入，并且备用放大器具有连接到第二参考电压的负输入。第一参考电压大于第二参考电压。第一晶体管具有连接到有源放大器的输出端的栅极和连接到电压调节输出的漏极，并且第二晶体管具有连接到备用放大器的输出端的栅极和连接到稳压输出端的漏极。电容器连接在芯片使能信号和稳压输出之间。

3. 发明授权

US08045374B2 Erase verification method of flash memory by selectively assigning deselected sectors 有权
标题翻译：通过选择性地分配未选择的扇区来擦除闪存的验证方法
公开(公告)号：US08045374B2
公开(公告)日：2011-10-25
申请号：US12689235
申请日：2010-01-19
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： G11C16/34
CPC分类号： G11C16/344 , G11C16/3445
摘要： A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller in the flash memory apparatus selectively assigns at least one of de-selected sectors instead of all of the de-selected sectors to perform the ERSV. Therefore, by managing the ERSV operation on the flash memory, the time for the ERSV operation thereon is reduced.
摘要翻译：提供了一种与传统的ERSV方法不同的闪速存储装置的适当擦除验证（ERSV）方法。也就是说，通过在至少一次擦除操作之后在闪速存储器上管理ERSV操作，快闪存储器装置中的闪速存储器控制器选择性地分配去选择的扇区中的至少一个而不是所有去选择的扇区，以执行 ERSV。因此，通过管理闪速存储器上的ERSV操作，减少了对其进行ERSV操作的时间。

4. 发明申请

US20090189638A1 LEVEL SHIFTER CIRCUIT 有权
标题翻译：水平更换电路
公开(公告)号：US20090189638A1
公开(公告)日：2009-07-30
申请号：US12021075
申请日：2008-01-28
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： H03K19/094
CPC分类号： H03K3/356182 , G11C5/145 , G11C16/12
摘要： A level shifter comprises a voltage converting circuit, a voltage pull-up circuit, and a control signal generating circuit. The voltage converting circuit is configured to receive an input signal of a first voltage level and to output an output signal of a second voltage level. The voltage pull-up circuit is coupled to the voltage converting circuit and configured to expeditiously pull up a voltage of an output node of the level shifter to the second voltage level in response to a control signal. The control signal generating circuit is configured to receive the input signal and to provide the control signal to the voltage pull-up circuit. The control signal generating circuit includes three transistors.A level shifter comprises a first-stage voltage converting circuit, a second-stage voltage converting circuit, and a voltage pull-up circuit. The first-stage voltage converting circuit is configured to receive an input signal of a first voltage level and to output a midway signal of an intermediate voltage level. The second-stage voltage converting circuit is configured to receive the midway signal and to output an output signal of a second voltage level. The voltage pull-up circuit is coupled to the second-stage voltage converting circuit and configured to expeditiously pull up a voltage of an output node of the level shifter to the second voltage level in response to a control signal with the intermediate voltage level.
摘要翻译：电平移位器包括电压转换电路，电压上拉电路和控制信号发生电路。电压转换电路被配置为接收第一电压电平的输入信号并输出第二电压电平的输出信号。电压上拉电路耦合到电压转换电路并且被配置为响应于控制信号而将电平移位器的输出节点的电压迅速上拉到第二电压电平。控制信号发生电路被配置为接收输入信号并且向电压上拉电路提供控制信号。控制信号发生电路包括三个晶体管。电平移位器包括第一级电压转换电路，第二级电压转换电路和电压上拉电路。第一级电压转换电路被配置为接收第一电压电平的输入信号并输出中间电压电平的中途信号。第二级电压转换电路被配置为接收中途信号并输出第二电压电平的输出信号。电压上拉电路耦合到第二级电压转换电路，并且被配置为响应于具有中间电压电平的控制信号而将电平移位器的输出节点的电压迅速上拉到第二电压电平。

5. 发明申请

US20080192545A1 FLASH MEMORY WITH SEQUENTIAL PROGRAMMING 有权
标题翻译：具有顺序编程的闪存
公开(公告)号：US20080192545A1
公开(公告)日：2008-08-14
申请号：US11674215
申请日：2007-02-13
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/12
摘要： A method of programming a group of memory cells in a semiconductor memory device selecting a group of memory cells for programming, and enabling a first subgroup of memory cells from the group of memory cells for programming. After enabling the first subgroup, the programming method waits a first predetermined time period and after the first predetermined time period, enables a second subgroup of memory cells from the group of memory cells for programming while continuing to enable the first subgroup for programming.
摘要翻译：一种在半导体存储器件中编程一组存储器单元的方法，所述半导体存储器件选择用于编程的存储器单元组，以及使得能够从所述存储器单元组中的第一存储器单元组进行编程。在启用第一子组之后，编程方法等待第一预定时间段，并且在第一预定时间段之后，使来自存储器单元组的存储器单元的第二子组用于编程，同时继续使第一子组能够进行编程。

6. 发明授权

US07277329B2 Erase method to reduce erase time and to prevent over-erase 有权
标题翻译：擦除方法可以减少擦除时间并防止过度擦除
公开(公告)号：US07277329B2
公开(公告)日：2007-10-02
申请号：US11297085
申请日：2005-12-08
申请人： Chung-Zen Chen , Chung-Shan Kuo
发明人： Chung-Zen Chen , Chung-Shan Kuo
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C16/16 , G11C16/3472
摘要： An erase method used in an array of flash memory cells arranged in a plurality of sectors provides each sector with an erase flag. The erase flag of sectors to be erased are set to a first value. The memory cells are sequentially verified from a first sector to a last sector whose flag is set to the first value and for each sector from a first address to a last address. When verification fails and the number of the same-cell-verifications is less than a predetermined number, the method applies an erase pulse and verifies the memory call at the same memory address again. When verification fails and the number of same-cell-verifications reaches the predetermined number, the remaining sectors whose flag is set to the first value are verified. When each memory cell of a sector to be erased passes verification, the erase flag of the sector is set to a second value. When the flag of each sector to be erased is set to the second value, the erase operation is terminated.
摘要翻译：在布置在多个扇区中的闪存单元阵列中使用的擦除方法为每个扇区提供擦除标志。要擦除的扇区的擦除标志被设置为第一值。存储器单元从第一扇区到其标志被设置为第一值的最后扇区以及从第一地址到最后地址的每个扇区被顺序地验证。当验证失败并且相同小区验证的数量小于预定数量时，该方法应用擦除脉冲并再次在相同存储器地址处验证存储器调用。当验证失败并且同一单元验证的数量达到预定数量时，验证标志被设置为第一值的剩余扇区。当要擦除的扇区的每个存储单元通过验证时，扇区的擦除标志被设置为第二值。当要擦除的每个扇区的标志被设置为第二值时，擦除操作终止。

7. 发明授权

US06909627B2 Apparatus turning on word line decoder by reference bit line equalization 有权
标题翻译：通过参考位线均衡开启字线解码器的装置
公开(公告)号：US06909627B2
公开(公告)日：2005-06-21
申请号：US10640388
申请日：2003-08-14
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： G11C8/08 , G11C8/10 , G11C11/418 , G11C11/00
CPC分类号： G11C8/08 , G11C8/10 , G11C11/418
摘要： A memory comprising a memory array, a plurality of word lines, a plurality of bit lines, a word line decoder, an equalizer and an equalization control apparatus is provided to meet the requirement of the completion of bit line equalization prior to the turn on of word lines. The memory array is arranged in columns and rows. The word lines are connected to the rows of the memory array. The bit lines connected to the columns of the memory array. The word line decoder is connected to the word lines for selecting one of the word lines. The equalizer is connected to the bit lines for equalizing the bit lines to a desired voltage. The equalization control apparatus serves for monitoring the equalizer to disable the word line decoder when the equalizer performs a equalization operation and enable the word line decoder when the equalization operation is completed.
摘要翻译：提供包括存储器阵列，多个字线，多个位线，字线解码器，均衡器和均衡控制装置的存储器，以满足在开启之前完成位线均衡的要求字线。存储器阵列以列和行排列。字线连接到存储器阵列的行。连接到存储器阵列的位线。字线解码器连接到用于选择字线之一的字线。均衡器连接到位线，以将位线均衡到期望的电压。均衡控制装置用于在均衡器执行均衡操作时监视均衡器以禁用字线解码器，并且当均衡操作完成时允许字线解码器。

8. 发明授权

US06137301A EPROM used as a voltage monitor for semiconductor burn-in 失效
标题翻译： EPROM用作半导体老化的电压监视器
公开(公告)号：US06137301A
公开(公告)日：2000-10-24
申请号：US75745
申请日：1998-05-11
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： G01R31/28 , G01R31/02
CPC分类号： G01R31/2849
摘要： In the present invention is described the use of an EPROM that is configred in a special way to monitor in situ the applied voltage to semiconductor product in a bun-in test and capture the maximum value of the applied voltage during the test. This technique operates off the threshold shift mechanism in which gate bias induces electrons at the substrate surface which are accelerated by the drain and trapped in the polysilcon gate after the electrons overcome the gate oxide energy barrier. This puts an extra bias on the gate making a threshold voltage shift. The measurement of the threshold voltage shift for a particular period of time will be proportional to the value of the applied voltage. The trapped electrons can be released back to the substrate by use of ultra violet light since the electrons gain energy from the UV light to overcome the gate oxide energy barrier.
摘要翻译：在本发明中描述了以特殊方式配置的EPROM的用途，以便在测试中原位监测施加到半导体产品的电压，并且在测试期间捕获施加的电压的最大值。该技术操作门限偏移机制，其中栅极偏压在衬底表面上感应电子，其在电子克服栅极氧化物能量势垒之后被漏极加速并被捕获在聚硅栅极中。这对栅极产生了额外的偏压，产生阈值电压偏移。在特定时间段内的阈值电压偏移的测量将与施加电压的值成比例。捕获的电子可以通过使用紫外线释放回到基板，因为电子从紫外光中获得能量以克服栅极氧化物能量势垒。

9. 发明授权

US5501998A Method for fabricating dynamic random access memory cells having vertical sidewall stacked storage capacitors 失效
标题翻译：用于制造具有垂直侧壁堆叠存储电容器的动态随机存取存储器单元的方法
公开(公告)号：US5501998A
公开(公告)日：1996-03-26
申请号：US233768
申请日：1994-04-26
申请人： Chung-Zen Chen
发明人： Chung-Zen Chen
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A new method for fabricating a microminiature capacitor, on a dynamic random access memory (DRAM) cell, using a single masking level was accomplished. The method involves opening the self-aligned node contact and the area for the bottom electrode of the capacitor, at the same time, using one masking level. The planarization of a low flow temperature glass (BPSG) and an etch back technique is used to define the bottom electrode of the capacitor, which is self-aligned to the etched opening. The resulting capacitor has vertical side walls on the perimeter of the capacitor plate, which increases its area without increasing the lateral area on the DRAM cell. Using one masking level for the fabrication of the capacitor, also eliminates the need to add additional space for the tolerance of a second mask.
摘要翻译：完成了在动态随机存取存储器（DRAM）单元上使用单个掩蔽级制造微型电容器的新方法。该方法包括打开自对准节点接触和电容器底部电极的面积，同时使用一个屏蔽电平。使用低流动温度玻璃（BPSG）和回蚀刻技术的平面化来限定电容器的底部电极，其与蚀刻开口自对准。所得电容器在电容器板的周边上具有垂直侧壁，这增加了其面积，而不增加DRAM单元上的横向面积。使用一个屏蔽电平来制造电容器，也消除了为第二个掩模的公差增加额外空间的需要。

10. 发明授权

US08456922B2 Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage 有权
公开(公告)号：US08456922B2
公开(公告)日：2013-06-04
申请号：US13477431
申请日：2012-05-22
申请人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/16
CPC分类号： G11C16/14 , G11C16/02 , G11C16/0408 , G11C16/08 , G11C16/16
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

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