会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • METHOD FOR BLOCKING THE EXECUTION OF A HACKING PROCESS
    • 阻止黑客进程执行的方法
    • US20120254998A1
    • 2012-10-04
    • US13394112
    • 2010-07-29
    • Jae Hwang LeeYoung Hwan KimDong Woo Shin
    • Jae Hwang LeeYoung Hwan KimDong Woo Shin
    • G06F21/00
    • G06F21/51
    • The present invention discloses a method of blocking the execution of a hacking process. In the method, a security process selects a process to be tested. The security process extracts the pattern of the process to be tested and compares it with hack diagnosis references. If the pattern of the process to be tested is included in the hack diagnosis references, the security process determines that the process to be tested is a hacking process. The security process calculates the unique hash value of the hacking process and compares it with hack blocking references. If the unique hash value of the hacking process is included in the hack blocking references, the security process blocks the execution of the hacking process, and, if the unique hash value of the hacking process is not included in the hack blocking references, the security process does not block the execution of the hacking process.
    • 本发明公开了一种阻止黑客进程执行的方法。 在该方法中,安全过程选择要测试的过程。 安全过程提取要测试过程的模式,并将其与黑客诊断参考进行比较。 如果被测试过程的模式包含在黑客诊断参考中,则安全过程确定要测试的过程是一个黑客进程。 安全过程计算黑客进程的唯一哈希值,并将其与黑客阻塞引用进行比较。 如果黑客入侵进程的唯一哈希值包含在黑客拦截引用中,则安全过程将阻止黑客进程的执行,并且如果黑客攻击进程的唯一哈希值不包括在黑客拦截引用中,则安全性 进程不会阻止黑客进程的执行。
    • 6. 发明授权
    • Metal nanoparticle having a self-assembled monolayer on its surface, and formation of conductive pattern using the same
    • 在其表面上具有自组装单层的金属纳米颗粒,以及使用其形成导电图案
    • US07923110B2
    • 2011-04-12
    • US11653889
    • 2007-01-17
    • Jong Jin ParkDong Woo ShinSung Woong Kim
    • Jong Jin ParkDong Woo ShinSung Woong Kim
    • B32B5/16
    • G03F7/0047B05D1/185C03C17/06H05K3/02H05K2201/0257H05K2203/0514Y10S977/777Y10S977/778Y10S977/779Y10T428/2991
    • A metal nanoparticle which is prepared by forming a self-assembled monolayer including a terminal reactive group on the surface thereof, and introducing a functional group capable of being removed by the action of an acid or an base into the terminal reactive group wherein the self-assembled monolayer is built up of a thiol, an isocyanide, an amine, a carboxylate or a phosphate compound having the terminal reactive group, or built up of a thiol, an isocyanide, an amine, a carboxylate or a phosphate compound having no terminal reactive group followed by introducing the terminal reactive group thereto; and a method for forming a conductive pattern using the same are provided. Since the metal nanoparticle of exemplary embodiments of the present invention can easily form a high conductive film or a high conductive pattern through photo-irradiation and photo-degradation and randomly regulate its conductivity when occasions demand, it can be advantageously applied to an antistatic washable sticky film, antistatic shoes, a conductive polyurethane printer roller, an electromagnetic interference shielding, and the like.
    • 一种金属纳米颗粒,其通过在其表面上形成包括末端反应性基团的自组装单层并将能够通过酸或碱的作用除去的官能团引入末端反应性基团而制备, 组装的单层由硫醇,异氰化物,胺,羧酸酯或具有末端反应性基团的磷酸酯化合物构成,或由硫醇,异氰化物,胺,羧酸酯或不具有末端反应性的磷酸酯化合物 然后引入末端反应性基团; 并且提供了使用其形成导电图案的方法。 由于本发明的示例性实施方案的金属纳米颗粒可以通过光照射和光降解容易地形成高导电膜或高导电图案,并且当需要时随机调节其导电性,因此可以有利地应用于抗静电可洗粘性 薄膜,抗静电鞋,导电性聚氨酯打印辊,电磁干扰屏蔽等。
    • 8. 发明授权
    • Clock control circuit for Rambus DRAM
    • Rambus DRAM的时钟控制电路
    • US06772359B2
    • 2004-08-03
    • US09725896
    • 2000-11-30
    • Jong Tae KwakDong Woo ShinJong Sup BaekChoul Hee KooNak Kyu Park
    • Jong Tae KwakDong Woo ShinJong Sup BaekChoul Hee KooNak Kyu Park
    • G06F104
    • G06F1/3275G06F1/3203G11C7/22G11C11/4076Y02D10/13Y02D10/14
    • A clock control circuit for a Rambus DRAM is provided which reduces power consumption by determining in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only during the read or current control command. Our circuit includes: an input signal detecting unit for generating an enable signal when one of a first comparing signal comparing an address value of the selected Rambus DRAM with a device address value of a COLC packet, and a second comparing signal comparing the address value of the selected Rambus DRAM with a device address value of a COLX packet is enabled, and when the command is a read or current control command; a signal generating unit for generating a clock enable signal for externally outputting an internal data when one of the first and second comparing signals is enabled; an output signal maintaining unit for outputting a control signal for maintaining the clock enable signal to the signal generating unit in the read or current control command; and an output signal control unit for outputting a control signal for controlling generation of the clock enable signal to the signal generating unit, when the command is not the read or current control command.
    • 提供了一种用于Rambus DRAM的时钟控制电路,其通过预先确定所应用的命令是读取还是当前控制命令来降低功耗,并且仅在读取或当前控制命令期间启用用于外部输出内部数据的时钟信号。 我们的电路包括:输入信号检测单元,用于当将所选择的Rambus DRAM的地址值与COLC分组的设备地址值进行比较的第一比较信号中的一个产生使能信号,以及第二比较信号, 所选择的具有COLX分组的设备地址值的Rambus DRAM被使能,并且当命令是读取或当前控制命令时; 信号产生单元,用于当所述第一和第二比较信号之一被使能时,产生用于外部输出内部数据的时钟使能信号; 输出信号维持单元,用于在读取或当前控制命令中输出用于将时钟使能信号保持到信号生成单元的控制信号; 以及输出信号控制单元,用于当命令不是读取或当前控制命令时,向信号生成单元输出用于控制产生时钟使能信号的控制信号。
    • 9. 发明授权
    • Controlling reading from and writing to a semiconductor memory device
    • 控制对半导体存储器件的读取和写入
    • US06442077B2
    • 2002-08-27
    • US09751394
    • 2001-01-02
    • Dong Woo Shin
    • Dong Woo Shin
    • G11C700
    • G11C7/24G11C7/1045G11C11/4076G11C11/4078
    • The inventions herein feature an arrangement for controlling read and write operations in a semiconductor memory device, which can reduce power consumption by controlling data read and write operations in a DRAM having an open drain output buffer. The circuit for controlling the read and write operations in the semiconductor memory device includes a write unit for comparing potential states of bits of a write data according to a control signal, converting the write data into a first logic level and writing the converted data on DRAMs as an internal data with a flag bit having a first logic level, when a number of the bits having the first logic level is greater than a number of the bits having a second logic level, and writing the write data on the DRAMs as an internal data with a flag bit having the second logic level, when the number of the bits having the first logic level is equal to or smaller than the number of the bits having the second logic level. A read unit reads a read data read from the DRAMs, or converts the read data and reads the converted data according to the potential state of the flag bit.
    • 本发明的特征在于一种用于控制半导体存储器件中的读和写操作的装置,其可以通过控制具有开漏输出缓冲器的DRAM中的数据读和写操作来降低功耗。 用于控制半导体存储器件中的读和写操作的电路包括写入单元,用于根据控制信号比较写入数据的位的电位状态,将写入数据转换成第一逻辑电平并将转换的数据写入DRAM 作为具有第一逻辑电平的标志位的内部数据,当具有第一逻辑电平的位的数量大于具有第二逻辑电平的位的数量时,并将写数据写入DRAM作为内部 当具有第一逻辑电平的比特数等于或小于具有第二逻辑电平的比特数时,具有具有第二逻辑电平的标志位的数据。 读取单元读取从DRAM读取的读取数据,或者转换读取的数据,并根据标志位的潜在状态读取转换的数据。