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1. 发明授权

US10923170B2 Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines 有权
公开(公告)号：US10923170B2
公开(公告)日：2021-02-16
申请号：US16358414
申请日：2019-03-19
申请人： Everspin Technologies, Inc.
发明人： Jason Janesky , Syed M. Alam , Dimitri Houssameddine , Mark Deherrera
IPC分类号： G11C11/16 , G11C29/12 , G11C29/02 , G11C29/50 , G11C17/16
摘要： Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

2. 发明授权

US10199122B2 Short detection and inversion 有权
公开(公告)号：US10199122B2
公开(公告)日：2019-02-05
申请号：US15852678
申请日：2017-12-22
申请人： Everspin Technologies Inc.
发明人： Thomas Andre , Jon Slaughter , Dimitri Houssameddine , Syed M. Alam
IPC分类号： G06F7/02 , H03M13/00 , G11C29/50 , G11C11/16 , G06F11/08 , G06F11/10 , G11C29/04
摘要： In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

3. 发明授权

US09721637B2 Method of writing to a spin torque magnetic random access memory 有权
公开(公告)号：US09721637B2
公开(公告)日：2017-08-01
申请号：US15167123
申请日：2016-05-27
申请人： Everspin Technologies, Inc.
发明人： Dimitri Houssameddine
IPC分类号： G11C11/00 , G11C11/16 , G11C13/00
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1673 , G11C13/0002 , G11C13/0097
摘要： A method for determining an optimized write pattern for low write error rate operation of a spin torque magnetic random access memory. The method provides a way to optimize the write error rate without affecting the memory speed. The method comprises one or more write pulses. The pulses may be independent in amplitude, duration and shape. Various exemplary embodiments adjust the write pattern based on the memory operating conditions, for example, operating temperature.

4. 发明授权

US09679627B2 Write verify programming of a memory device 有权
公开(公告)号：US09679627B2
公开(公告)日：2017-06-13
申请号：US14502367
申请日：2014-09-30
申请人： Everspin Technologies, Inc.
发明人： Thomas Andre , Dimitri Houssameddine , Syed M. Alam , Jon Slaughter , Chitra Subramanian
IPC分类号： G11C16/04 , G11C11/16 , G06F12/0804
CPC分类号： G11C11/1675 , G06F12/0804 , G11C11/1677 , Y02D10/13
摘要： A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

5. 发明授权

US09548095B2 Redundant magnetic tunnel junctions in magnetoresistive memory 有权
标题翻译：磁阻记忆体中的冗余磁隧道结
公开(公告)号：US09548095B2
公开(公告)日：2017-01-17
申请号：US14697577
申请日：2015-04-27
申请人： Everspin Technologies, Inc.
发明人： Dimitri Houssameddine , Jon Slaughter
IPC分类号： G11C11/00 , G11C11/16 , G11C29/00
CPC分类号： G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1695 , G11C11/1697 , G11C29/70 , G11C29/74 , G11C29/838 , G11C2213/78 , G11C2213/79
摘要： Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.
摘要翻译：自旋扭矩磁随机存取存储器（MRAM）中的存储单元包括每个存储器单元内的至少两个磁性隧道结，其中每个存储器单元仅存储单个数据位的信息。耦合到存储器单元的访问电路即使当存储单元内的磁隧道结之一有缺陷并且不再起作用时，也能够读取和写入存储单元。自参考和参考读取可以与多个磁性隧道结存储器单元结合使用。在一些实施例中，向存储器单元的写入迫使所有磁隧道结进入已知状态，而在其它实施例中，磁性隧道结的子集被强制为已知状态。

6. 发明授权

US09419208B2 Magnetoresistive memory element and method of fabricating same 有权
标题翻译：磁阻存储元件及其制造方法
公开(公告)号：US09419208B2
公开(公告)日：2016-08-16
申请号：US15046483
申请日：2016-02-18
申请人： Everspin Technologies, Inc.
发明人： Renu Whig , Jijun Sun , Nicholas Rizzo , Jon Slaughter , Dimitri Houssameddine , Frederick Mancoff
IPC分类号： H01L29/82 , H01L43/08 , H01L43/02 , H01L43/10 , G11C11/16
CPC分类号： H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
摘要： A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
摘要翻译：磁阻存储元件（例如，自旋转矩磁阻存储元件）包括固定磁性层，具有垂直磁各向异性的自由磁性层和设置在固定磁性层和自由磁性层之间的第一电介质。第一电介质的第一表面与自由磁性层的第一表面接触。磁阻存储元件还包括第二电介质，其具有与自由磁性层的第二表面接触的第一表面，包括导电材料的导体以及设置在第二电介质和导体之间的电极。电极包括：（i）具有与第二电介质的第二表面接触的表面的非铁磁部分，和（ii）第二部分，其包括设置在第二电介质的非铁磁部分之间的至少一个铁磁材料电极和导体。

7. 发明申请

US20160093354A1 SHORT DETECTION AND INVERSION 有权
标题翻译：短期检测和反转
公开(公告)号：US20160093354A1
公开(公告)日：2016-03-31
申请号：US14502287
申请日：2014-09-30
申请人： Everspin Technologies, Inc.
发明人： Thomas Andre , Jon Slaughter , Dimitri Houssameddine , Syed M. Alam
IPC分类号： G11C11/16 , G06F11/08
CPC分类号： G11C29/50 , G06F11/08 , G06F11/1048 , G11C11/1673 , G11C2029/0411
摘要： In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
摘要翻译：在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配位单元格。

8. 发明授权

US11757451B2 Systems and methods for configuration of a configuration bit with a value 有权
公开(公告)号：US11757451B2
公开(公告)日：2023-09-12
申请号：US17652905
申请日：2022-02-28
申请人： Everspin Technologies, Inc.
发明人： Dimitri Houssameddine , Syed M. Alam , Sanjeev Aggarwal
IPC分类号： H03K19/1776 , G11C11/16 , G11C13/00 , H03K19/17784 , H03K19/17724 , G06F21/78
CPC分类号： H03K19/1776 , G11C11/1675 , G11C13/0069 , H03K19/17724 , H03K19/17784 , G06F21/78
摘要： The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.

9. 发明授权

US10622554B2 Magnetoresistive stack and method of fabricating same 有权
公开(公告)号：US10622554B2
公开(公告)日：2020-04-14
申请号：US16419165
申请日：2019-05-22
申请人： EVERSPIN TECHNOLOGIES, INC.
发明人： Renu Whig , Jijun Sun , Nicholas Rizzo , Jon Slaughter , Dimitri Houssameddine , Frederick Mancoff
IPC分类号： H01L21/02 , H01L43/12 , H01L43/10 , H01L43/08 , H01L43/02 , G11C11/16
CPC分类号： H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
摘要： A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

10. 发明授权

US10614907B2 Short detection and inversion 有权
公开(公告)号：US10614907B2
公开(公告)日：2020-04-07
申请号：US16242892
申请日：2019-01-08
申请人： Everspin Technologies, Inc.
发明人： Thomas Andre , Jon Slaughter , Dimitri Houssameddine , Syed M. Alam
IPC分类号： G06F7/02 , H03M13/00 , G11C29/50 , G11C11/16 , G06F11/08 , G06F11/10 , G11C29/04
CPC分类号： G11C29/50 , G06F11/08 , G06F11/1048 , G11C11/1673 , G11C2029/0411
摘要： In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

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