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1. 发明授权

US08806164B2 Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface 有权
标题翻译：与从第一接口到第二接口的操作过渡相关联的设备，电子设备和方法
公开(公告)号：US08806164B2
公开(公告)日：2014-08-12
申请号：US13041288
申请日：2011-03-04
申请人： Giulio Albini , Emanuele Confalonieri
发明人： Giulio Albini , Emanuele Confalonieri
IPC分类号： G06F12/00
CPC分类号： G06F12/1466 , G06F3/0622 , G06F3/0637 , G06F3/0673 , G06F3/0679 , G06F12/00 , G06F12/14 , G06F13/1668 , G06F13/4036 , G06F13/4221 , G06F2212/1052
摘要： Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.
摘要翻译：本文公开的主题涉及包括存储器和控制器的控制器，诸如控制器，其与共享至少一个存储器块的两个或多个接口之间的操作转换相关联地确定块锁定状态。该装置可以支持单通道或多通道存储器访问，写保护状态逻辑或各种接口优先级方案。

2. 发明授权

US08706957B2 Multi-partitioning of memories 有权
标题翻译：多分区记忆
公开(公告)号：US08706957B2
公开(公告)日：2014-04-22
申请号：US13620980
申请日：2012-09-15
申请人： Danilo Caraccio , Emanuele Confalonieri , Federico Tiziani
发明人： Danilo Caraccio , Emanuele Confalonieri , Federico Tiziani
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F3/0644 , G06F3/0607 , G06F3/0608 , G06F3/0631 , G06F3/0637 , G06F3/0685 , G06F9/5077 , G06F12/0223 , G06F12/0238 , G06F12/0246 , G06F13/385 , G06F2212/2022 , G06F2212/2024 , G06F2213/3804 , G06F2213/3854 , G11C13/0002 , G11C13/0004 , G11C14/009 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.
摘要翻译：各种实施例包括装置和方法，包括如由主机指导的在存储器装置中重新配置分区的方法。该方法包括通过第一接口控制器管理命令以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。描述附加的装置和方法。

3. 发明授权

US08599638B2 Multi-channel memory and power supply-driven channel selection 有权
标题翻译：多通道存储器和电源驱动通道选择
公开(公告)号：US08599638B2
公开(公告)日：2013-12-03
申请号：US13596822
申请日：2012-08-28
申请人： Emanuele Confalonieri
发明人： Emanuele Confalonieri
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C13/0004 , G11C16/04
摘要： Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.
摘要翻译：本文公开的主题涉及存储器件，更具体地涉及多通道存储器件以及选择其一个或多个通道的方法。

4. 发明授权

US07903478B1 High impedance reference voltage distribution 有权
标题翻译：高阻参考电压分布
公开(公告)号：US07903478B1
公开(公告)日：2011-03-08
申请号：US12355466
申请日：2009-01-16
申请人： Marco Sforzin , Emanuele Confalonieri
发明人： Marco Sforzin , Emanuele Confalonieri
IPC分类号： G11C7/00
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14
摘要： A sense amplifier may be used to measure voltages and/or currents that represent logic levels stored in memory cells of memory devices. Accuracy and stability of such measurements may be improved by selective switching to isolate sense amplifiers from other portions of a circuit.
摘要翻译：读出放大器可用于测量表示存储在存储器件的存储器单元中的逻辑电平的电压和/或电流。这种测量的精度和稳定性可以通过选择性地切换以将读出放大器与电路的其它部分隔离来提高。

5. 发明授权

US07782665B2 Method of managing a memory device employing three-level cells 有权
标题翻译：管理使用三电平单元的存储器件的方法
公开(公告)号：US07782665B2
公开(公告)日：2010-08-24
申请号：US12039268
申请日：2008-02-28
申请人： Paolo Turbanti , Carla Giuseppina Poidomani , Emanuele Confalonieri , Luigi Bettini
发明人： Paolo Turbanti , Carla Giuseppina Poidomani , Emanuele Confalonieri , Luigi Bettini
IPC分类号： G11C16/04
CPC分类号： G11C16/3436
摘要： A method of managing a multi-level memory device having singularly addressable three-level cells includes storing strings of three bits by coding them in corresponding ternary strings according to a coding scheme and writing each of the ternary strings in a respective pair of three-level cells. Strings of three bits are read by reading respective ternary strings written in respective pairs of three-level cells and decoding each read ternary string in a corresponding string of three bits according to the coding scheme. A pair of adjacent bits, belonging to at least one of a same initial string and two initial adjacent strings, are programmed by identifying pairs of three-level cells to be programmed that encode the strings of three bits and programming each pair of three-level cells.
摘要翻译：一种管理具有奇异寻址的三电平单元的多电平存储器件的方法包括通过根据编码方案将它们编码在相应的三进制字符串中来存储三位字符串，并将三个字符串中的每一个写入相应的一对三电平细胞。通过读取写在相应的三电平单元对中的各个三进制字符串来读取三位字符串，并根据编码方案对相应的三位串中的每个读取三进制串进行解码。属于相同初始串和两个初始相邻串中的至少一个的一对相邻位通过识别对要编程的三电平单元的对来编程，所述三电平单元对三位串进行编程，并对每一对三电平进行编程细胞。

6. 发明授权

US07352645B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07352645B2
公开(公告)日：2008-04-01
申请号：US11250176
申请日：2005-10-13
申请人： Marco Sforzin , Emanuele Confalonieri , Nicola Del Gatto , Carla Giuseppina Poidomani
发明人： Marco Sforzin , Emanuele Confalonieri , Nicola Del Gatto , Carla Giuseppina Poidomani
IPC分类号： G11C7/00
CPC分类号： G11C16/24 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of said plurality. The semiconductor memory device further includes a bit line selection structure for selecting at least one among said bit lines and a voltage clamping circuit structure adapted to cause the clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to a selected bit line during a read operation.
摘要翻译：提供半导体存储器件。半导体存储器件包括具有多个存储单元的存储器矩阵，存储器单元根据多个行排列，多个列和多个位线，每个位线与所述多个的至少一个相应的列相关联。半导体存储器件还包括位线选择结构，用于选择所述位线中的至少一个和钳位电路结构，该钳位电路结构适于在一段时间内将与选定位线相邻且电容耦合的非选定位线的规定电压钳位读操作。

7. 发明授权

US06788586B2 Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same 有权
标题翻译：具有输出信号切换噪声降低的非易失性存储器的输出缓冲器和包括该缓冲器的非易失性存储器
公开(公告)号：US06788586B2
公开(公告)日：2004-09-07
申请号：US10161053
申请日：2002-05-30
申请人： Emanuele Confalonieri , Antonino Geraci , Marco Sforzin , Lorenzo Bedarida
发明人： Emanuele Confalonieri , Antonino Geraci , Marco Sforzin , Lorenzo Bedarida
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1051
摘要： Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.
摘要翻译：这里描述的是一个输出缓冲器，它包括一个由上拉晶体管和一个下拉晶体管形成的输出级，它们串联连接在一个设在电源电位的电源线和一个设在地电位的地线之间，中间节点连接到输出缓冲区的输出。输出缓冲器还包括布置在输出缓冲器的输出端和上拉晶体管之间的单向解耦级，用于在输出缓冲器的切换瞬变期间使输出从电源线分离，以防止存在开关噪声后者被传送到输出缓冲器的输出。

8. 发明授权

US09852781B2 Dynamically allocable regions in non-volatile memories 有权
公开(公告)号：US09852781B2
公开(公告)日：2017-12-26
申请号：US12703626
申请日：2010-02-10
申请人： Emanuele Confalonieri , Giuseppe Russo , Luca Porzio
发明人： Emanuele Confalonieri , Giuseppe Russo , Luca Porzio
IPC分类号： G11C11/00 , G11C8/12 , G11C13/00
CPC分类号： G11C8/12 , G11C13/0004 , G11C13/0064 , G11C13/0069
摘要： An embodiment of a non-volatile memory device is proposed. Said memory device comprises a matrix of memory cells; each memory cell is individually programmable to at least a first logic level and individually erasable to a second logic level. The memory device further comprises partition means for logically subdividing the matrix into a plurality of subspaces; each subspace comprises at least one respective memory cell. The memory device further comprises selection means for selecting a subspace, operative means for performing an operation on all the memory cells of the selected subspace, and means for dynamically modifying the number of subspaces and/or the number of memory cells included in each subspace.

9. 发明授权

US08856487B2 Configurable partitions for non-volatile memory 有权
标题翻译：用于非易失性存储器的可配置分区
公开(公告)号：US08856487B2
公开(公告)日：2014-10-07
申请号：US13556066
申请日：2012-07-23
申请人： Emanuele Confalonieri , Corrado Villa
发明人： Emanuele Confalonieri , Corrado Villa
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F12/0246 , G06F2212/7201 , G06F2212/7208
摘要： Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.
摘要翻译：用于配置非易失性存储器设备的示例性实施例可以包括将非易失性存储器的M个物理分区配置为两个或更多个存储体，其中两个或多个存储体分别包括M个物理分区中的一个或多个，并且其中至少一个 M个物理分区中的第一个包括第一大小，并且其中至少第二个M个物理分区包括第二大小。

10. 发明授权

US08762656B2 Temperature alert and low rate refresh for a non-volatile memory 有权
标题翻译：非易失性存储器的温度警报和低速刷新
公开(公告)号：US08762656B2
公开(公告)日：2014-06-24
申请号：US13142418
申请日：2008-12-30
申请人： Emanuele Confalonieri , Daniele Balluchi
发明人： Emanuele Confalonieri , Daniele Balluchi
IPC分类号： G06F13/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0033 , G11C16/3431
摘要： A method and apparatus are described for measuring a temperature within a non-volatile memory, storing, in a register within the non-volatile memory, a temperature alert comprising one or more bits indicating the non-volatile memory has exceeded a threshold temperature for a period of time, determining, by a host, that the temperature alert is active, and in response to the determination that the temperature alert is active, refreshing at least a portion of the non-volatile memory.
摘要翻译：描述了一种用于测量非易失性存储器内的温度的方法和装置，其在非易失性存储器内的寄存器中存储包括指示非易失性存储器的一个或多个位的温度警报已超过阈值温度时间段，由主机确定温度警报是活动的，并且响应于温度警报激活的确定，刷新至少一部分非易失性存储器。

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