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1. 发明授权

US08149616B2 Method for multilevel programming of phase change memory cells using adaptive reset pulses 有权
标题翻译：使用自适应复位脉冲对相变存储单元进行多电平编程的方法
公开(公告)号：US08149616B2
公开(公告)日：2012-04-03
申请号：US12780580
申请日：2010-05-14
申请人： Ferdinando Bedeschi , Claudio Resta , Enzo Michele Donze , Roberto Gastaldi , Alessandro Cabrini , Guido Torelli
发明人： Ferdinando Bedeschi , Claudio Resta , Enzo Michele Donze , Roberto Gastaldi , Alessandro Cabrini , Guido Torelli
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C2013/0076 , G11C2013/0092
摘要： A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or more set pulse, a size of the conductive path defining a programmed state of the PCM cell and an output electrical quantity associated thereto, and being controlled by the value of the reset pulse and set pulse. The step of forming an amorphous region envisages adaptively and iteratively determining, during the programming operations, a value of the reset pulse optimized for electrical and/or physical properties of the PCM cell, and in particular determining a minimum amplitude value of the reset pulse, which allows programming a desired programmed state and a desired value of the output electrical quantity.
摘要翻译：用于编程多电平PCM单元的方法设想：通过施加一个或多个复位脉冲，在PCM单元的存储元件中形成非晶相变材料的非晶区域; 以及通过施加一个或多个设定脉冲，形成所述PCM单元的编程状态的导电路径的大小和与其相关联的输出电量，并通过所述值来控制所述晶体相变材料的导电路径通过所述非晶区域的复位脉冲和设定脉冲。形成非晶区域的步骤设想在编程操作期间自适应地和迭代地确定针对PCM单元的电气和/或物理特性优化的复位脉冲的值，特别是确定复位脉冲的最小振幅值，这允许编程期望的编程状态和输出电量的期望值。

2. 发明授权

US07936584B2 Reading phase change memories 有权
标题翻译：阅读相变记忆
公开(公告)号：US07936584B2
公开(公告)日：2011-05-03
申请号：US12354425
申请日：2009-01-15
申请人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
发明人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
IPC分类号： G11C11/06
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.
摘要翻译：可以使用高达阈值相变存储器元件的读取电流来读取元件而不对存储元件进行阈值化。在某些情况下，较高的电流可能会改善性能。由于读取元素并且在触发存储器元件之前停止了当前存储器元件，因此存储器元件不会被阈值。

3. 发明申请

US20100165712A1 METHOD FOR LOW-STRESS MULTILEVEL READING OF PHASE CHANGE MEMORY CELLS AND MULTILEVEL PHASE CHANGE MEMORY 有权
标题翻译：用于低相位多相读取相变记忆体和多相位变化记忆的方法
公开(公告)号：US20100165712A1
公开(公告)日：2010-07-01
申请号：US12345398
申请日：2008-12-29
申请人： Ferdinando Bedeschi , Claudio Resta , Marco Ferraro
发明人： Ferdinando Bedeschi , Claudio Resta , Marco Ferraro
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0076
摘要： According to a method for multilevel reading of a phase change memory cell a bit line (9) and a PCM cell (2) are first selected and a first bias voltage (VBL, V00) is applied to the selected bit line (9). A first read current (IRD00), that flows through the selected bit line (9) in response to the first bias voltage (VBL, V00), is compared with a first reference current (I00). The first reference current (I00) is such that the first read current (IRD00) is lower than the first reference current (I00), when the selected PCM cell (2) is in a reset state, and is otherwise greater. It is then determined whether the selected PCM cell (2) is in the reset state, based on comparing the first read current (IRD00) with the first reference current (I00). A second bias voltage (VBL, V01), greater than the first bias voltage (VBL, V00), is applied to the selected bit line (9) if the selected PCM cell (2) is not in the reset state.
摘要翻译：根据用于相变存储单元的多电平读取的方法，首先选择位线（9）和PCM单元（2），并且将第一偏置电压（VBL，V00）施加到所选择的位线（9）。将响应于第一偏置电压（VBL，V00）流过所选位线（9）的第一读取电流（IRD00）与第一参考电流（I00）进行比较。当选择的PCM单元（2）处于复位状态时，第一参考电流（I00）使得第一读取电流（IRD00）低于第一参考电流（I00），否则更大。基于将第一读取电流（IRD00）与第一参考电流（I00）进行比较，确定所选择的PCM单元（2）是否处于复位状态。如果所选PCM单元（2）不处于复位状态，则将大于第一偏置电压（VBL，V00）的第二偏置电压（VBL，V01）施加到所选位线（9）。

4. 发明申请

US20090080242A1 Programming a multilevel phase change memory cell 有权
标题翻译：编程多级相变存储单元
公开(公告)号：US20090080242A1
公开(公告)日：2009-03-26
申请号：US11904306
申请日：2007-09-26
申请人： Claudio Resta , Marco Ferraro , Ferdinando Bedeschi , Alessandro Cabrini
发明人： Claudio Resta , Marco Ferraro , Ferdinando Bedeschi , Alessandro Cabrini
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0078 , G11C2013/0092
摘要： Multilevel phase change memory cells may be programmed forming amorphous regions of amorphous phase change material in a storage region of the phase change memory cell. Crystalline paths of crystalline phase change material are formed through the amorphous regions of amorphous phase change material. Lengths of the crystalline paths are controlled so that at least a first crystalline path has a first length in a first programming state and a second crystalline path has a second length, different from the first length, in a second programming state.
摘要翻译：多级相变存储器单元可以被编程为在相变存储单元的存储区域中形成无定形相变材料的非晶区域。通过非晶相变材料的非晶区形成结晶相变材料的结晶路径。控制晶体路径的长度，使得至少第一晶体路径在第二编程状态下具有处于第一编程状态的第一长度，并且第二晶体路径具有与第一长度不同的第二长度。

5. 发明授权

US07388775B2 Detecting switching of access elements of phase change memory cells 有权
标题翻译：检测相变存储单元存取单元的切换
公开(公告)号：US07388775B2
公开(公告)日：2008-06-17
申请号：US11527147
申请日：2006-09-26
申请人： Ferdinando Bedeschi , Claudio Resta , Ward D. Parkinson , Roberto Gastaldi
发明人： Ferdinando Bedeschi , Claudio Resta , Ward D. Parkinson , Roberto Gastaldi
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C7/062 , G11C7/08 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0054 , G11C2013/0071 , G11C2213/76
摘要： A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.
摘要翻译：存储器包括由相变材料制成的用于存储逻辑值的存储元件（OUM）和响应于存储单元的选择从较高电阻状态切换到较低电阻状态的存取元件（OTS），较高电阻条件下的存取元件将存储元件与读取电路分离，并将该存储元件耦合到读取电路的较低电阻条件。读取电路包括读出放大器，用于根据与存储器单元相关联的电量确定存储单元中存储的逻辑值。读取电路还包括检测器，其通过与延迟波形进行比较来检测接入元件的切换，或者检测列变化率的变化;以及电路，用于响应于检测到的切换访问元素

6. 发明授权

US07257039B2 Bit line discharge control method and circuit for a semiconductor memory 有权
标题翻译：半导体存储器的位线放电控制方法和电路
公开(公告)号：US07257039B2
公开(公告)日：2007-08-14
申请号：US10971776
申请日：2004-10-22
申请人： Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi
发明人： Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi
IPC分类号： G11C7/00
CPC分类号： G11C13/0004 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C15/00 , G11C29/02 , G11C29/025 , G11C29/83 , G11C2213/79
摘要： A method of controlling a discharge of bit lines of a matrix of memory cells comprises conditioning a value of a current flowing through a bit line of the matrix during a bit line discharge phase to an absence of an indication of defectiveness of the bit line. The method allows preventing crowbar currents that otherwise flow during the bit line discharge phase when a defective bit line exhibits a short-circuit to a defective word line.
摘要翻译：控制存储器单元的矩阵的位线的放电的方法包括在位线放电阶段期间调节流过矩阵的位线的电流的值，使得不存在位线的缺陷的指示。该方法允许当有缺陷的位线与缺陷字线短路时，防止在位线放电阶段期间流过的撬棒电流。

7. 发明授权

US07154774B2 Detecting switching of access elements of phase change memory cells 有权
标题翻译：检测相变存储单元存取单元的切换
公开(公告)号：US07154774B2
公开(公告)日：2006-12-26
申请号：US11093709
申请日：2005-03-30
申请人： Ferdinando Bedeschi , Claudio Resta , Ward D. Parkinson , Roberto Gastaldi
发明人： Ferdinando Bedeschi , Claudio Resta , Ward D. Parkinson , Roberto Gastaldi
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C7/062 , G11C7/08 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0054 , G11C2013/0071 , G11C2213/76
摘要： A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.
摘要翻译：存储器包括由相变材料制成的用于存储逻辑值的存储元件（OUM）和响应于存储单元的选择从较高电阻状态切换到较低电阻状态的存取元件（OTS），较高电阻条件下的存取元件将存储元件与读取电路分离，并将该存储元件耦合到读取电路的较低电阻条件。读取电路包括读出放大器，用于根据与存储器单元相关联的电量确定存储单元中存储的逻辑值。读取电路还包括检测器，其通过与延迟波形进行比较来检测接入元件的切换，或者检测列变化率的变化;以及电路，用于响应于检测到的切换访问元素

8. 发明申请

US20060227592A1 Reading phase change memories 有权
公开(公告)号：US20060227592A1
公开(公告)日：2006-10-12
申请号：US11093878
申请日：2005-03-30
申请人： Ward Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
发明人： Ward Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.

9. 发明申请

US20050047193A1 Phase -change memory device with biasing of deselected bit lines 有权
标题翻译：具有取消选择位线偏置的交换存储器件
公开(公告)号：US20050047193A1
公开(公告)日：2005-03-03
申请号：US10926784
申请日：2004-08-25
申请人： Ferdinando Bedeschi , Claudio Resta
发明人： Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C7/12 , G11C16/02 , G11C11/00
CPC分类号： G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2213/79
摘要： A memory device is proposed. The memory device includes a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a functional element with a programmable resistivity and a unidirectional conduction access element connected in series, a plurality of word lines and a plurality of bit lines, the memory cells of each row being connected to a corresponding word line and the memory cells of each column being connected to a corresponding bit line, means for driving the bit lines to a desired voltage, means for selecting at least one bit line in an operative condition of the memory device, each selected bit line being connected to the means for driving and each deselected bit line being disconnected from the means for driving, and means for selecting a word line in the operative condition, each access element associated with the selected word line and the at least one selected bit line being forward biased and the other access elements being reverse biased; the memory device further includes means for biasing the deselected bit lines in the operative condition to prevent a leakage current of the reverse biased access elements from forward biasing the access elements associated with the selected word line and the deselected bit lines.
摘要翻译：提出了一种存储器件。存储器件包括布置成多行和多列的存储器单元矩阵，每个存储单元包括具有可编程电阻率的功能元件和串联连接的单向导通存取元件，多个字线和多个每行的存储单元连接到对应的字线，并且每列的存储单元连接到对应的位线，用于将位线驱动到期望电压的装置，用于选择至少一个位的装置在存储器件的操作状态下，每个选定的位线连接到用于驱动的装置，并且每个取消选择的位线与用于驱动的装置断开，以及用于在操作状态中选择字线的装置，每个存取元件相关联与所选择的字线和所述至少一个所选择的位线被正向偏置，并且其他存取元件被反向偏置; 存储器件还包括用于在操作状态下偏置未选择的位线的装置，以防止反向偏置的存取元件的泄漏电流向前偏置与所选择的字线和取消选择的位线相关联的存取元件。

10. 发明申请

US20160162213A1 METHODS FOR OPERATING A MEMORY ARRAY 有权
标题翻译：操作存储阵列的方法
公开(公告)号：US20160162213A1
公开(公告)日：2016-06-09
申请号：US15012478
申请日：2016-02-01
申请人： Ferdinando Bedeschi , Claudio Resta , Marco Ferraro
发明人： Ferdinando Bedeschi , Claudio Resta , Marco Ferraro
IPC分类号： G06F3/06 , G11C13/00
CPC分类号： G06F3/0622 , G06F3/0643 , G06F3/0679 , G11C13/0004 , G11C13/004 , G11C13/0059 , G11C13/0069 , G11C13/0097 , G11C13/02 , H01L45/04 , H01L45/06
摘要： Methods of operating memory arrays are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored, and writing the pattern to the memory array. Other methods of operation are also described.
摘要翻译：描述操作存储器阵列的方法。在各种实施例中，一种方法包括确定要写入存储器阵列的模式，该模式包括具有要存储的敏感信息的数据位和具有与要存储的敏感信息不重要的状态的数据位，以及写入模式到内存数组。还描述了其他操作方法。

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