专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06399896B1 Circuit package having low modulus, conformal mounting pads 失效
标题翻译：具有低模数，适形安装垫的电路封装
公开(公告)号：US06399896B1
公开(公告)日：2002-06-04
申请号：US09525379
申请日：2000-03-15
申请人： Frank J. Downes, Jr. , Donald S. Farquhar , Robert M. Japp , William J. Rudik
发明人： Frank J. Downes, Jr. , Donald S. Farquhar , Robert M. Japp , William J. Rudik
IPC分类号： H05K116
CPC分类号： H05K3/326 , H05K1/0271 , H05K1/111 , H05K1/114 , H05K2201/0133 , H05K2201/0187 , H05K2201/10734 , H05K2203/0307
摘要： Reliability of circuit packaging while accommodating larger chips and increased temperature excursions is achieved by use of compliant pads only at the locations of connections between packaging levels, preferably between a laminated chip carrier and a printed circuit board. The invention allows the coefficient of thermal expansion of the chip carrier to be economically well-matched to the CTE of the chip and accommodation of significant differences in CTEs of package materials to be accommodated at a single packaging level. The compliant pads are preferably of low aspect ratio which are not significantly deflected by accelerations and can be formed on a surface or recessed into it. Connections can be made through surface connections and/or plated through holes. Connection enhancements such as solder wettable surfaces or dendritic textures are provided in a conductive metal or alloy layer over a compliant rubber or elastomer layer which may be conductive or non-conductive.
摘要翻译：通过仅在封装层之间的连接位置（优选在层压芯片载体和印刷电路板之间）使用柔性焊盘来实现电路封装的可靠性，同时容纳更大的芯片和增加的温度漂移。本发明允许芯片载体的热膨胀系数与芯片的CTE经济地良好匹配，并且可以容纳在单个封装层面上容纳的封装材料的CTE的显着差异。柔性衬垫优选地具有低纵横比，其不被加速度显着偏转，并且可以形成在表面上或凹入其中。可以通过表面连接和/或电镀通孔进行连接。在导电金属或合金层中的柔性橡胶或弹性体层上提供诸如焊料可润湿表面或树枝状织构的连接增强，其可以是导电的或不导电的。

2. 发明授权

US06834426B1 Method of fabricating a laminate circuit structure 失效
标题翻译：制造层叠电路结构的方法
公开(公告)号：US06834426B1
公开(公告)日：2004-12-28
申请号：US09625135
申请日：2000-07-25
申请人： Robert M. Japp , Gregory A. Kevern , William J. Rudik
发明人： Robert M. Japp , Gregory A. Kevern , William J. Rudik
IPC分类号： H05K320
CPC分类号： H05K3/4641 , H05K3/4069 , H05K3/445 , H05K3/4614 , H05K2201/09536 , H05K2201/096 , H05K2201/09881 , H05K2201/10378 , Y10T29/49126 , Y10T29/49128 , Y10T29/49165
摘要： A method for fabricating a laminate circuit structure is provided. The method comprises: providing at least two modularized circuitized voltage plane subassemblies wherein each of the subassemblies comprise at least two signal planes having an external and internal surface disposed about an internal voltage plane; providing a dielectric material between the signal and voltage planes; and providing dielectric on each external surface of each signal plane; and providing a non-cured or partially cured curable dielectric composition between the subassemblies wherein the dielectric composition comprises, dielectric material that is of the same material as the dielectric material used in said subassemblies, aligning the subassemblies, and then laminating to cause bonding of the subassemblies.
摘要翻译：提供一种制造叠层电路结构的方法。该方法包括：提供至少两个模块化的电路化电压平面子组件，其中每个子组件包括至少两个具有围绕内部电压平面设置的外部和内部表面的信号平面; 在信号和电压平面之间提供介电材料; 并在每个信号平面的每个外表面上提供电介质; 并且在所述子组件之间提供未固化或部分固化的可固化电介质组合物，其中所述电介质组合物包括与所述子组件中使用的介电材料具有相同材料的介电材料，对准所述子组件，然后层压以引起子组件

3. 发明授权

US5126192A Flame retardant, low dielectric constant microsphere filled laminate 失效
标题翻译：阻燃剂，低介电常数微胶囊填充层压板
公开(公告)号：US5126192A
公开(公告)日：1992-06-30
申请号：US470453
申请日：1990-01-26
申请人： Leroy N. Chellis , Robert M. Japp , William J. Summa , William J. Rudik , David W. Wang
发明人： Leroy N. Chellis , Robert M. Japp , William J. Summa , William J. Rudik , David W. Wang
IPC分类号： B32B5/00 , C08J5/24 , C08K7/24 , H05K1/03 , H05K3/46
CPC分类号： C08J5/24 , C08K7/24 , H05K1/0373 , H05K1/0366 , H05K2201/012 , H05K2201/0209 , H05K2201/0239 , H05K2201/0254 , Y10S428/901 , Y10T428/24917 , Y10T428/25 , Y10T428/2982 , Y10T428/31663
摘要： A flame retardant, low dielectric constant, controlled coefficient of thermal expansion, low cost prepreg material which includes randomly distributed silane coated hollow microspheres has been prepared by standard impregnation and lamination techniques. Laminates made of this prepreg can be drilled cleanly for through holes and can be used as a substrate for surface mounted devices.

4. 发明授权

US06845557B2 Method for producing an electronic package possessing controlled impedance characteristics 失效
标题翻译：具有控制阻抗特性的电子封装的制造方法
公开(公告)号：US06845557B2
公开(公告)日：2005-01-25
申请号：US10225862
申请日：2002-08-22
申请人： Thomas R. Miller , William J. Rudik , Robert J. Testa , Kevin P. Unger , Michael Wozniak
发明人： Thomas R. Miller , William J. Rudik , Robert J. Testa , Kevin P. Unger , Michael Wozniak
IPC分类号： H01L23/498 , H01L23/66 , H05K1/02 , H05K3/24 , H05K3/40 , H05K3/46 , H01K3/10
CPC分类号： H05K3/4623 , H01L23/49822 , H01L23/66 , H01L2924/0002 , H01L2924/3011 , H05K1/0237 , H05K3/246 , H05K3/4069 , H05K3/4652 , H05K2201/0347 , H05K2201/0352 , H05K2201/0355 , H05K2203/0554 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method for creating an impedance controlled printing wiring board, particularly the formation of a structure for high speed printed wiring boards incorporating multiple differential impedance controlled layers. Furthermore, disclosed is the provision of a method for producing an impedance controlled printed circuit wiring board. Also, there is the provision of a method for producing high speed printed wiring boards with multiple differential impedance controlled layers.
摘要翻译：一种用于产生阻抗控制印刷线路板的方法，特别是形成包含多个差分阻抗控制层的高速印刷线路板的结构。此外，公开了提供一种制造阻抗控制印刷电路布线板的方法。此外，提供了一种用于生产具有多个差分阻抗控制层的高速印刷线路板的方法。

5. 发明授权

US06699736B2 Electrical coupling of a stiffener to a chip carrier 有权
标题翻译：加强筋与芯片载体的电耦合
公开(公告)号：US06699736B2
公开(公告)日：2004-03-02
申请号：US10305643
申请日：2002-11-26
申请人： Terry J. Dornbos , Raymond A. Phillips, Jr. , Mark V. Pierson , William J. Rudik , David L. Thomas
发明人： Terry J. Dornbos , Raymond A. Phillips, Jr. , Mark V. Pierson , William J. Rudik , David L. Thomas
IPC分类号： H01L2144
CPC分类号： H05K3/0061 , H01L21/4846 , H05K3/386 , H05K3/4038 , H05K2201/0305 , H05K2201/09554 , H05K2201/10977
摘要： A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate. The electrically conductive contact may include an electrically conductive adhesive or a metallic solder. Additional embodiments of the present invention form the adhesive layer by applying an electrically conductive adhesive on the substrate, wherein after the stiffener is placed on the adhesive layer, the electrically conductive adhesive mechanically and electrically couples the stiffener to the surface of the substrate.
摘要翻译：用于将金属加强件导电耦合到芯片载体的方法和结构。衬底在其表面上具有导电焊盘，并且在衬底表面上形成粘合剂层。金属加强件被放置在粘合剂层上，其中粘合剂层将加强件机械地连接到基底表面，并将加强件电耦合到垫。然后将粘合剂层固化，例如通过在升高的温度下加压。本发明的实施例通过在焊盘上形成导电触点并在基板上设置干燥的粘合剂来形成粘合剂层，使得导电触点位于干粘合剂中的孔内。导电触头将加强件电耦合到焊盘。固化步骤包括固化干燥粘合剂和导电接触，导致干燥粘合剂将加强剂粘合到基底上。导电接触可包括导电粘合剂或金属焊料。本发明的另外的实施方案通过在基底上施加导电粘合剂形成粘合剂层，其中在将加强件放置在粘合剂层上之后，导电粘合剂将加强件机械地和电耦合到基底的表面。

6. 发明授权

US4855333A Multiple wire photosensitive adhesive for wire embedment 失效
标题翻译：用于电线嵌入的多线感光胶
公开(公告)号：US4855333A
公开(公告)日：1989-08-08
申请号：US35207
申请日：1987-04-06
申请人： William J. Rudik , George P. Schmitt , John F. Shipley
发明人： William J. Rudik , George P. Schmitt , John F. Shipley
IPC分类号： C09J163/10 , H05K3/10 , H05K3/38 , H05K3/46 , H05K7/06
CPC分类号： H05K7/06 , C09J163/10 , H05K3/386 , H05K2201/0195 , H05K2201/10287 , H05K3/103 , H05K3/4626 , Y10T428/31511 , Y10T428/31525 , Y10T428/31529
摘要： A high density dimensionally stable encapsulated wire circuit board and a method of making such a board is described. A photo-curable adhesive having a unique combination of rheological properties is utilized to bond insulated wires to a substrate. The unique combination of rheological properties of the adhesive used in the encapsulated wire circuit boards of this invention include a specified range of values for the Storage Shear Modulus and specified range of values for the Loss Angle ratio.A new photo-curable adhesive having these properties and a method of obtaining such an adhesive are also described.
摘要翻译：描述了高密度尺寸稳定的封装线电路板和制造这种板的方法。使用具有流变特性的独特组合的光固化粘合剂将绝缘导线粘合到基底上。在本发明的封装线路板中使用的粘合剂的流变特性的独特组合包括存储剪切模量的特定值范围和损失角比的值的特定范围。还描述了具有这些性质的新型可光固化粘合剂和获得这种粘合剂的方法。

7. 发明授权

US07547577B2 Method of making circuitized substrate with solder paste connections 有权
标题翻译：用锡膏连接制作电路化基板的方法
公开(公告)号：US07547577B2
公开(公告)日：2009-06-16
申请号：US11598647
申请日：2006-11-14
申请人： Norman A. Card , Thomas R. Miller , William J. Rudik
发明人： Norman A. Card , Thomas R. Miller , William J. Rudik
IPC分类号： H01L21/44
CPC分类号： H05K3/4614 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05644 , H01L2224/16225 , H05K3/3484 , H05K2203/061 , H05K2203/063 , H05K2203/1572 , Y10T29/49126 , Y10T29/49147 , Y10T29/49158 , H01L2924/00014 , H01L2924/013
摘要： A method of making a circuitized substrate assembly in which two or more subassemblies are aligned and bonded together. The bonding, preferably using lamination, results in effective electrical connections being formed between respective pairs of conductors of the subassemblies in such a manner that the metallurgies of the conductors, and those of an interim metallic solder paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies is forced to flow to engage and surround the conductor coupling, without adversely affecting the electrical connection formed.
摘要翻译：一种制造电路化基板组件的方法，其中两个或更多个子组件对准并结合在一起。优选使用层压的结合导致在子组件的各对导体之间形成有效的电连接，使得导体和中间金属焊膏的导体的冶金被有效地混合，并且可流动的中间电介质在配合子组件之间使用的流体被迫流动以接合和围绕导体耦合，而不会不利地影响形成的电连接。

8. 发明授权

US4544801A Circuit board including multiple wire photosensitive adhesive 失效
标题翻译：电路板包括多线感光胶
公开(公告)号：US4544801A
公开(公告)日：1985-10-01
申请号：US639152
申请日：1984-08-09
申请人： William J. Rudik , George P. Schmitt , John F. Shipley
发明人： William J. Rudik , George P. Schmitt , John F. Shipley
IPC分类号： C09J163/10 , H05K3/10 , H05K3/38 , H05K3/46 , H05K7/06 , H05K1/03
CPC分类号： H05K7/06 , C09J163/10 , H05K3/386 , H05K2201/0195 , H05K2201/10287 , H05K3/103 , H05K3/4626
摘要： A high density dimensionally stable encapsulated wire circuit board and a method of making such a board is described. A photo-curable adhesive having a unique combination of rheological properties is utilized to bond insulated wires to a substrate. The unique combination of rheological properties of the adhesive used in the encapsulated wire circuit boards of this invention include a specified range of values for the Storage Shear Modulus and specified range of values for the Loss Angle ratio.
摘要翻译：描述了高密度尺寸稳定的封装线电路板和制造这种板的方法。使用具有流变特性的独特组合的光固化粘合剂将绝缘导线粘合到基底上。在本发明的封装线路板中使用的粘合剂的流变特性的独特组合包括存储剪切模量的特定值范围和损失角比的值的特定范围。

9. 发明申请

US20080110016A1 Method of making circuitized substrate with solder paste connections 有权
标题翻译：用锡膏连接制作电路化基板的方法
公开(公告)号：US20080110016A1
公开(公告)日：2008-05-15
申请号：US11598647
申请日：2006-11-14
申请人： Norman A. Card , Thomas R. Miller , William J. Rudik
发明人： Norman A. Card , Thomas R. Miller , William J. Rudik
IPC分类号： H05K3/36 , H05K1/11
CPC分类号： H05K3/4614 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05644 , H01L2224/16225 , H05K3/3484 , H05K2203/061 , H05K2203/063 , H05K2203/1572 , Y10T29/49126 , Y10T29/49147 , Y10T29/49158 , H01L2924/00014 , H01L2924/013
摘要： A method of making a circuitized substrate assembly in which two or more subassemblies are aligned and bonded together. The bonding, preferably using lamination, results in effective electrical connections being formed between respective pairs of conductors of the subassemblies in such a manner that the metallurgies of the conductors, and those of an interim metallic solder paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies is forced to flow to engage and surround the conductor coupling, without adversely affecting the electrical connection formed.
摘要翻译：一种制造电路化基板组件的方法，其中两个或更多个子组件对准并结合在一起。优选使用层压的结合导致在子组件的各对导体之间形成有效的电连接，使得导体和中间金属焊膏的导体的冶金被有效地混合，并且可流动的中间电介质在配合子组件之间使用的流体被迫流动以接合和围绕导体耦合，而不会不利地影响形成的电连接。

10. 发明授权

US06781064B1 Printed circuit boards for electronic device packages having glass free non-conductive layers and method of forming same 失效
标题翻译：具有无玻璃非导电层的电子器件封装的印刷电路板及其形成方法
公开(公告)号：US06781064B1
公开(公告)日：2004-08-24
申请号：US09342584
申请日：1999-06-29
申请人： Bernd K. Appelt , Anilkumar C. Bhatt , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , William J. Rudik , William E. Wilson
发明人： Bernd K. Appelt , Anilkumar C. Bhatt , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , William J. Rudik , William E. Wilson
IPC分类号： H05K103
CPC分类号： H01L23/564 , H01L21/481 , H01L23/498 , H01L23/49894 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H05K1/036 , H05K1/0366 , H05K3/429 , H05K3/4626 , H05K3/4641 , H05K2201/0195 , H05K2201/0769 , H05K2201/09718 , H05K2201/09881 , H01L2924/00014 , H01L2924/00012
摘要： A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.
摘要翻译：一种用于诸如球栅阵列封装或有机芯片载体封装的电子器件封装中的印刷电路板。该印刷电路板包括一个无玻璃的电介质，用于分离和绝缘电源芯，电路或电镀通孔，以防止导电材料沿玻璃基预浸料衬底迁移引起的短路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式