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1. 发明申请

US20090175000A1 Halogen-free circuitized substrate with reduced thermal expansion, method of making same, multilayered substrate structure utilizing same, and information handling system utilizing same 有权
标题翻译：具有减少热膨胀的无卤素电路化基板，其制造方法，利用其的多层基板结构以及利用其的信息处理系统
公开(公告)号：US20090175000A1
公开(公告)日：2009-07-09
申请号：US12380618
申请日：2009-03-02
申请人： Robert M. Japp , Voya R. Markovich , Kostas I. Papthomas
发明人： Robert M. Japp , Voya R. Markovich , Kostas I. Papthomas
IPC分类号： H05K7/00 , H05K3/30
CPC分类号： H05K3/4688 , H01L23/145 , H01L23/3733 , H01L23/49833 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2924/3011 , H05K1/0366 , H05K1/0373 , H05K3/4652 , H05K3/4655 , H05K2201/0209 , H05K2201/0278 , H05K2201/09309 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , H01L2224/0401
摘要： A circuitized substrate including a composite layer comprising a first dielectric sub-layer comprised of a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein. A method of making such a substrate is also provided, as is a multilayered assembly including one or more such circuitized substrates, possibly in combination with other substrates. An information handling system designed for having one or more such circuitized substrates is also provided.
摘要翻译：一种电路化基板，包括复合层，该复合层包括由不含卤素的树脂和分散在其中的纤维构成的第一介电子层和不含纤维的第二电介质子层，并且还包括无卤素树脂和无机颗粒。还提供了制造这种基板的方法，以及包括一个或多个这样的电路化基板的多层组件，可能与其它基板组合。还提供了设计用于具有一个或多个这样的电路化基板的信息处理系统。

2. 发明申请

US20090173426A1 Multilayered circuitized substrate with p-aramid dielectric layers and method of making same 失效
标题翻译：具有对芳族聚酰胺介电层的多层电路基板及其制造方法
公开(公告)号：US20090173426A1
公开(公告)日：2009-07-09
申请号：US12380617
申请日：2009-03-02
申请人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
发明人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
IPC分类号： B32B37/12 , B44C1/22
CPC分类号： H01L23/145 , H01L23/3733 , H01L23/3735 , H01L23/4922 , H01L23/49822 , H01L23/49827 , H01L23/564 , H01L2924/0002 , H01L2924/12044 , H05K1/0366 , H05K1/0373 , H05K3/4602 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0209 , H05K2201/0278 , H05K2201/068 , Y10T29/4913 , Y10T156/10 , H01L2924/00
摘要： A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
摘要翻译：一种多层电路化基板，包括多个介电层，每个电介质层由浸渍有不含卤素的低吸湿性树脂的对芳族聚酰胺纸构成，所述不含卤素的低吸湿性树脂包括无机填料，但不包括连续或半连续的玻璃纤维作为其一部分，电路层位于第一介电层上。还提供了制造该基板的方法。

3. 发明申请

US20080191354A1 Circuitized substrate with p-aramid dielectric layers and method of making same 失效
标题翻译：具有对位芳族聚酰胺介电层的电路基板及其制造方法
公开(公告)号：US20080191354A1
公开(公告)日：2008-08-14
申请号：US12081051
申请日：2008-04-10
申请人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
发明人： Robert M. Japp , Voya R. Markovich , Kostas I. Papathomas , Mark D. Poliks
IPC分类号： H01L23/50 , H05K3/30
CPC分类号： H01L23/145 , H01L23/3733 , H01L23/3735 , H01L23/4922 , H01L23/49822 , H01L23/49827 , H01L23/564 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/12044 , H01L2924/15311 , H05K1/0366 , H05K1/0373 , H05K3/4602 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0209 , H05K2201/0278 , H05K2201/068 , Y10T29/4913 , H01L2224/0401
摘要： A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on the dielectric layer. A method of making this substrate is also provided.
摘要翻译：一种电路化基板，包括具有浸渍有无卤低吸湿树脂的对芳族聚酰胺纸，并且不包括作为其一部分的连续或半连续玻璃纤维纤维的介电层和位于介电层上的第一电路层。还提供了制造该基板的方法。

4. 发明申请

US20080168651A1 Method of providing a printed circuit board with an edge connection portion and/or a plurality of cavities therein 有权
标题翻译：在其中提供具有边缘连接部分和/或多个空腔的印刷电路板的方法
公开(公告)号：US20080168651A1
公开(公告)日：2008-07-17
申请号：US11652633
申请日：2007-01-12
申请人： Ashwinkumar C. Bhatt , Robert J. Harendza , Robert M. Japp
发明人： Ashwinkumar C. Bhatt , Robert J. Harendza , Robert M. Japp
IPC分类号： H05K3/36
CPC分类号： H05K1/117 , H05K1/112 , H05K3/4611 , H05K2201/09127 , H05K2201/0919 , H05K2201/09472 , H05K2201/09845 , H05K2203/061 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49165 , Y10T29/49169
摘要： A method of making a printed circuit board in which at least three substrates are aligned and bonded together (e.g., using lamination). Two of the substrates have openings formed therein, with each opening including a cover member located therein. During lamination, the cover members for a seal and prevent dielectric material (e.g., resin) liquefied during the lamination from contacting the conductive layers on the opposed surfaces of the inner (first) substrate. A PCB is thus formed with either a projecting edge portion or a plurality of cavities therein such that electrical connection may be made to the PCB using an edge connector or the like.
摘要翻译：制造印刷电路板的方法，其中至少三个基板被对准并结合在一起（例如，使用层压）。两个基板具有形成在其中的开口，每个开口包括位于其中的盖构件。在层压期间，用于密封和防止介电材料（例如树脂）的盖构件在层压期间液化以接触内（第一）衬底的相对表面上的导电层。因此，PCB在其中形成有突出边缘部分或多个空腔，使得可以使用边缘连接器等对PCB进行电连接。

5. 发明授权

US06996903B2 Formation of multisegmented plated through holes 失效
公开(公告)号：US06996903B2
公开(公告)日：2006-02-14
申请号：US10641182
申请日：2003-08-14
申请人： Donald S. Farquhar , Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
发明人： Donald S. Farquhar , Robert M. Japp , John M. Lauffer , Konstantinos I. Papathomas
IPC分类号： H01K3/10
CPC分类号： H05K3/429 , H05K2201/0187 , H05K2201/096 , H05K2201/09645 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24917
摘要： A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.

6. 发明授权

US06834426B1 Method of fabricating a laminate circuit structure 失效
标题翻译：制造层叠电路结构的方法
公开(公告)号：US06834426B1
公开(公告)日：2004-12-28
申请号：US09625135
申请日：2000-07-25
申请人： Robert M. Japp , Gregory A. Kevern , William J. Rudik
发明人： Robert M. Japp , Gregory A. Kevern , William J. Rudik
IPC分类号： H05K320
CPC分类号： H05K3/4641 , H05K3/4069 , H05K3/445 , H05K3/4614 , H05K2201/09536 , H05K2201/096 , H05K2201/09881 , H05K2201/10378 , Y10T29/49126 , Y10T29/49128 , Y10T29/49165
摘要： A method for fabricating a laminate circuit structure is provided. The method comprises: providing at least two modularized circuitized voltage plane subassemblies wherein each of the subassemblies comprise at least two signal planes having an external and internal surface disposed about an internal voltage plane; providing a dielectric material between the signal and voltage planes; and providing dielectric on each external surface of each signal plane; and providing a non-cured or partially cured curable dielectric composition between the subassemblies wherein the dielectric composition comprises, dielectric material that is of the same material as the dielectric material used in said subassemblies, aligning the subassemblies, and then laminating to cause bonding of the subassemblies.
摘要翻译：提供一种制造叠层电路结构的方法。该方法包括：提供至少两个模块化的电路化电压平面子组件，其中每个子组件包括至少两个具有围绕内部电压平面设置的外部和内部表面的信号平面; 在信号和电压平面之间提供介电材料; 并在每个信号平面的每个外表面上提供电介质; 并且在所述子组件之间提供未固化或部分固化的可固化电介质组合物，其中所述电介质组合物包括与所述子组件中使用的介电材料具有相同材料的介电材料，对准所述子组件，然后层压以引起子组件

7. 发明授权

US06459047B1 Laminate circuit structure and method of fabricating 失效
标题翻译：层压电路结构及其制造方法
公开(公告)号：US06459047B1
公开(公告)日：2002-10-01
申请号：US09947130
申请日：2001-09-05
申请人： Robert M. Japp , Voya R. Markovich , Konstantinos I. Papathomas
发明人： Robert M. Japp , Voya R. Markovich , Konstantinos I. Papathomas
IPC分类号： H05K109
CPC分类号： H05K3/382 , H05K1/056 , H05K3/383 , H05K3/384 , H05K3/388 , H05K3/389 , H05K3/445 , H05K2201/0209 , H05K2201/0355 , H05K2203/0307 , Y10S428/901 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.
摘要翻译：提供了基板和制造基板的方法。衬底包括金属层，其中具有至少一个通孔，金属层在其上具有粘附促进层。部分固化的低损失聚合物或聚合物前体层位于粘附促进层上，并且多个导电电路线位于部分固化的介电层的一部分上。衬底可以用作制造多层印刷电路板的构件。

8. 发明授权

US06399896B1 Circuit package having low modulus, conformal mounting pads 失效
标题翻译：具有低模数，适形安装垫的电路封装
公开(公告)号：US06399896B1
公开(公告)日：2002-06-04
申请号：US09525379
申请日：2000-03-15
申请人： Frank J. Downes, Jr. , Donald S. Farquhar , Robert M. Japp , William J. Rudik
发明人： Frank J. Downes, Jr. , Donald S. Farquhar , Robert M. Japp , William J. Rudik
IPC分类号： H05K116
CPC分类号： H05K3/326 , H05K1/0271 , H05K1/111 , H05K1/114 , H05K2201/0133 , H05K2201/0187 , H05K2201/10734 , H05K2203/0307
摘要： Reliability of circuit packaging while accommodating larger chips and increased temperature excursions is achieved by use of compliant pads only at the locations of connections between packaging levels, preferably between a laminated chip carrier and a printed circuit board. The invention allows the coefficient of thermal expansion of the chip carrier to be economically well-matched to the CTE of the chip and accommodation of significant differences in CTEs of package materials to be accommodated at a single packaging level. The compliant pads are preferably of low aspect ratio which are not significantly deflected by accelerations and can be formed on a surface or recessed into it. Connections can be made through surface connections and/or plated through holes. Connection enhancements such as solder wettable surfaces or dendritic textures are provided in a conductive metal or alloy layer over a compliant rubber or elastomer layer which may be conductive or non-conductive.
摘要翻译：通过仅在封装层之间的连接位置（优选在层压芯片载体和印刷电路板之间）使用柔性焊盘来实现电路封装的可靠性，同时容纳更大的芯片和增加的温度漂移。本发明允许芯片载体的热膨胀系数与芯片的CTE经济地良好匹配，并且可以容纳在单个封装层面上容纳的封装材料的CTE的显着差异。柔性衬垫优选地具有低纵横比，其不被加速度显着偏转，并且可以形成在表面上或凹入其中。可以通过表面连接和/或电镀通孔进行连接。在导电金属或合金层中的柔性橡胶或弹性体层上提供诸如焊料可润湿表面或树枝状织构的连接增强，其可以是导电的或不导电的。

9. 发明授权

US6142361A Chip C4 assembly improvement using magnetic force and adhesive 失效
标题翻译：芯片C4组装改进使用磁力和粘合剂
公开(公告)号：US6142361A
公开(公告)日：2000-11-07
申请号：US458483
申请日：1999-12-09
申请人： Francis J. Downes, Jr. , Robert M. Japp , Mark V. Pierson
发明人： Francis J. Downes, Jr. , Robert M. Japp , Mark V. Pierson
IPC分类号： H01L21/60 , H05K3/30 , H05K3/34 , B23K1/20 , B23K31/02
CPC分类号： H01L24/81 , B23K2201/40 , H01L2224/81801 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H05K3/303 , H05K3/3436 , Y10T29/4913 , Y10T29/53196
摘要： A method, and associated structure, for adhesively coupling a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is placed on a top surface of the chip. A temporary or permanent stiffener of ferrous material is placed on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier. Similarly, a magnetic force on the block is directed toward the magnet such that the electronic component and the chip carrier are held in alignment. The solder bump is reflowed at a temperature between the melting temperature of the solder bump and the melting temperature of the C4 solder structure. The reflowing reconfigures the solder bump. The magnetic force on the block frictionally clamps the reflowed solder between the C4 solder structure and the pad. The chip and carrier are cooled, resulting in the C4 solder structure being adhesively and conductively coupled to the pad.
摘要翻译：一种用于将芯片粘合地耦合到有机芯片载体的方法和相关联的结构。芯片通过在芯片上的C4焊料结构和芯片载体的顶表面上的焊盘之间接合焊料凸块来附接到有机芯片载体的顶表面。焊料凸点的熔化温度小于C4焊料结构的熔化温度。将一块黑色金属材料放置在芯片的上表面上。铁芯材料的临时或永久性加强件被放置在芯片载体的顶表面上。永磁体耦合到芯片载体的底表面。或者，可以使用电磁来代替电磁体。由于永磁体或电磁体，加强件上的磁力被引向磁体并且基本平坦化芯片载体的第一表面。类似地，块上的磁力指向磁体，使得电子部件和芯片载体保持对准。在焊料凸块的熔化温度和C4焊料结构的熔化温度之间的温度下回流焊料凸点。回流重新配置焊料凸块。块上的磁力摩擦地夹住C4焊料结构和焊盘之间的回流焊料。芯片和载体被冷却，导致C4焊料结构被粘性地导电耦合到焊盘。

10. 发明授权

US08499440B2 Method of making halogen-free circuitized substrate with reduced thermal expansion 有权
标题翻译：制造具有降低的热膨胀的无卤电路基板的方法
公开(公告)号：US08499440B2
公开(公告)日：2013-08-06
申请号：US12380618
申请日：2009-03-02
申请人： Robert M. Japp , Voya R. Markovich , Kostas I. Papthomas
发明人： Robert M. Japp , Voya R. Markovich , Kostas I. Papthomas
IPC分类号： H05K3/20 , H05K1/00
CPC分类号： H05K3/4688 , H01L23/145 , H01L23/3733 , H01L23/49833 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2924/3011 , H05K1/0366 , H05K1/0373 , H05K3/4652 , H05K3/4655 , H05K2201/0209 , H05K2201/0278 , H05K2201/09309 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , H01L2224/0401
摘要： A method of making a circuitized substrate including a composite layer having a first dielectric sub-layer including a halogen-free resin and fibers dispersed therein and a second dielectric sub-layer without fibers but also including a halogen-free resin with inorganic particulates therein.
摘要翻译：一种制造电路化基板的方法，该基板包括具有包含无卤素树脂的第一介电子层和分散在其中的纤维的复合层和不含纤维的第二电介质子层，并且还包括无卤素树脂和无机颗粒。

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