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1. 发明申请

US20110264946A1 MODULAR INTEGRATED CIRCUIT WITH CLOCK CONTROL CIRCUIT 有权
标题翻译：具有时钟控制电路的模块化集成电路
公开(公告)号：US20110264946A1
公开(公告)日：2011-10-27
申请号：US12767226
申请日：2010-04-26
申请人： Greg Goodemote , Khan Kibria , Mark N. Fullerton , Niray P. Dagli , Liang Deng , Sam Liu
发明人： Greg Goodemote , Khan Kibria , Mark N. Fullerton , Niray P. Dagli , Liang Deng , Sam Liu
IPC分类号： G06F1/08
CPC分类号： G06F1/26 , G06F1/06 , G06F1/08
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.
摘要翻译：模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。集线器模块包括耦合到多个集线器接口的时钟控制电路，其通过经由信号从多个辐条模块中的相应一个接收时钟请求信号来选择性地将多个时钟信号提供给多个辐条模块接口，响应于时钟请求信号产生多个时钟信号中的至少一个; 以及经由所述多个集线器接口中相应一个的所述信号接口将所述多个时钟信号中的至少一个发送到所述多个辐条模块中的对应的一个。

2. 发明授权

US08392745B2 Modular integrated circuit with clock control circuit 有权
标题翻译：具有时钟控制电路的模块化集成电路
公开(公告)号：US08392745B2
公开(公告)日：2013-03-05
申请号：US12767226
申请日：2010-04-26
申请人： Greg Goodemote , Khan Kibria , Mark N. Fullerton , Niray P. Dagli , Liang Deng , Sam Liu
发明人： Greg Goodemote , Khan Kibria , Mark N. Fullerton , Niray P. Dagli , Liang Deng , Sam Liu
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/06 , G06F1/08
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.
摘要翻译：模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。集线器模块包括耦合到多个集线器接口的时钟控制电路，其通过经由信号从多个辐条模块中的相应一个接收时钟请求信号来选择性地将多个时钟信号提供给多个辐条模块接口，响应于时钟请求信号产生多个时钟信号中的至少一个; 以及经由所述多个集线器接口中相应一个的所述信号接口将所述多个时钟信号中的至少一个发送到所述多个辐条模块中的对应的一个。

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