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1. 发明授权

US08392745B2 Modular integrated circuit with clock control circuit 有权
标题翻译：具有时钟控制电路的模块化集成电路
公开(公告)号：US08392745B2
公开(公告)日：2013-03-05
申请号：US12767226
申请日：2010-04-26
申请人： Greg Goodemote , Khan Kibria , Mark N. Fullerton , Niray P. Dagli , Liang Deng , Sam Liu
发明人： Greg Goodemote , Khan Kibria , Mark N. Fullerton , Niray P. Dagli , Liang Deng , Sam Liu
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/06 , G06F1/08
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.
摘要翻译：模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。集线器模块包括耦合到多个集线器接口的时钟控制电路，其通过经由信号从多个辐条模块中的相应一个接收时钟请求信号来选择性地将多个时钟信号提供给多个辐条模块接口，响应于时钟请求信号产生多个时钟信号中的至少一个; 以及经由所述多个集线器接口中相应一个的所述信号接口将所述多个时钟信号中的至少一个发送到所述多个辐条模块中的对应的一个。

2. 发明申请

US20110264946A1 MODULAR INTEGRATED CIRCUIT WITH CLOCK CONTROL CIRCUIT 有权
标题翻译：具有时钟控制电路的模块化集成电路
公开(公告)号：US20110264946A1
公开(公告)日：2011-10-27
申请号：US12767226
申请日：2010-04-26
申请人： Greg Goodemote , Khan Kibria , Mark N. Fullerton , Niray P. Dagli , Liang Deng , Sam Liu
发明人： Greg Goodemote , Khan Kibria , Mark N. Fullerton , Niray P. Dagli , Liang Deng , Sam Liu
IPC分类号： G06F1/08
CPC分类号： G06F1/26 , G06F1/06 , G06F1/08
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.
摘要翻译：模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。集线器模块包括耦合到多个集线器接口的时钟控制电路，其通过经由信号从多个辐条模块中的相应一个接收时钟请求信号来选择性地将多个时钟信号提供给多个辐条模块接口，响应于时钟请求信号产生多个时钟信号中的至少一个; 以及经由所述多个集线器接口中相应一个的所述信号接口将所述多个时钟信号中的至少一个发送到所述多个辐条模块中的对应的一个。

3. 发明授权

US08386688B2 Modular integrated circuit with common interface 失效
公开(公告)号：US08386688B2
公开(公告)日：2013-02-26
申请号：US12770690
申请日：2010-04-29
申请人： Mark N. Fullerton , Robert Morris , Lance Flake , Lawrence J. Madar, III , Sam Liu , Chaoyang Zhao , Vinay Bhasin , Joyjit Nath , Bhupesh Kharwa , Claude G. Hayek
发明人： Mark N. Fullerton , Robert Morris , Lance Flake , Lawrence J. Madar, III , Sam Liu , Chaoyang Zhao , Vinay Bhasin , Joyjit Nath , Bhupesh Kharwa , Claude G. Hayek
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F1/10 , G06F1/26 , G06F13/4027 , G06F2213/0038 , Y02D30/34
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

4. 发明申请

US20110271028A1 MODULAR INTEGRATED CIRCUIT WITH COMMON INTERFACE 失效
标题翻译：具有通用接口的模块化集成电路
公开(公告)号：US20110271028A1
公开(公告)日：2011-11-03
申请号：US12770690
申请日：2010-04-29
申请人： Mark N. Fullerton , Robert Morris , Lance Flake , Lawrence J. Madar, III , Sam Liu , Chaoyang Zhao , Vinay Bhasin , Joyjit Nath , Bhupesh Kharwa , Claude G. Hayek
发明人： Mark N. Fullerton , Robert Morris , Lance Flake , Lawrence J. Madar, III , Sam Liu , Chaoyang Zhao , Vinay Bhasin , Joyjit Nath , Bhupesh Kharwa , Claude G. Hayek
IPC分类号： G06F13/36 , G06F1/24
CPC分类号： G06F13/28 , G06F1/10 , G06F1/26 , G06F13/4027 , G06F2213/0038 , Y02D30/34
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.
摘要翻译：模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。所述多个集线器接口在所述集线器模块和所述多个辐条模块中的每一个之间提供多个信号接口，其中所述多个信号接口中的每一个与所述多个信号接口中的每一个信号接口隔离，并且其中多个信号接口中的每一个根据公共信令格式进行操作。

5. 发明申请

US20110009016A1 SNAP HOUSING FOR A MODULAR CONNECTOR ASSEMBLY 审中-公开
标题翻译：模块化连接器总成的SNAP住房
公开(公告)号：US20110009016A1
公开(公告)日：2011-01-13
申请号：US12498695
申请日：2009-07-07
申请人： Sam Liu , Aurielo Hernandez
发明人： Sam Liu , Aurielo Hernandez
IPC分类号： H01R13/46
CPC分类号： H01R13/506 , H01R13/6215
摘要： The present invention is directed to a snap housing for a modular connector assembly that includes a first body having first and second opposed surfaces, the second surface has a first profile, a portion of which is complementary to a profile of a first segment of the modular connector assembly; a second body having third and fourth opposed surfaces, the fourth surface having a second profile, a portion of which is complementary to a segment of a profile of a second segment of the modular connector assembly. The second surface faces the fourth surface; and a pair of spaced-apart fasteners is disposed between the first and second bodies to rotate or move horizontally with respect to the first and second bodies.
摘要翻译：本发明涉及用于模块化连接器组件的卡扣壳体，其包括具有第一和第二相对表面的第一本体，第二表面具有第一轮廓，其一部分与模块化的第一段的轮廓互补连接器组件具有第三和第四相对表面的第二主体，所述第四表面具有第二轮廓，所述第二轮廓的一部分与所述模块化连接器组件的第二段的轮廓段互补。第二表面面向第四表面; 并且一对间隔开的紧固件设置在第一和第二主体之间以相对于第一和第二主体水平地旋转或移动。

6. 发明授权

US07079717B2 Control circuit for IEEE 1394b optical transmission protocol 失效
标题翻译： IEEE 1394b光传输协议控制电路
公开(公告)号：US07079717B2
公开(公告)日：2006-07-18
申请号：US10766619
申请日：2004-01-28
申请人： Sam Liu , Yan Wang
发明人： Sam Liu , Yan Wang
IPC分类号： G02B6/14 , H04B10/08 , H04B10/00 , H03K5/22 , H03K3/12
CPC分类号： H03F3/45475
摘要： An On-Off control circuit between the IEEE1394a and IEEE1394b compliant physical layer (PHY) output driver circuitry and the glass fiber optical physical medium dependent (PMD) sub-layer within the architecture of the IEEE 1394b standard addresses the stability issue incurred by electronic circuit's inherent noise that interferes with the connection detecting procedure defined by the connection management protocol (CMP) of the IEEE 1394b standard. The circuit includes of a voltage divider to provide a reference voltage of about 50% of the output common mode voltage, a voltage comparator, and a feedback coupled to the positive input of the comparator to eliminate possible oscillation. The negative input of the comparator may be connected to the mid point of TPB termination network and the positive input of the comparator may be connected to the output of the voltage dividing circuit. The output of the comparator may be connected to the transmission enable bar input of the optical transceiver. In the process of connection detection, the common mode voltage of the TPB output toggles between 0 volt and 1.5 volt. Thus, the changing of the common mode voltage of TPB output driver circuitry will switch the optical transmitter on and off at a proper time to meet with the input signal definition requirements at the peer node according to the IEEE1394b standard.
摘要翻译： IEEE 1394a和IEEE1394b兼容物理层（PHY）输出驱动器电路和IEEE 1394b标准架构内的玻璃光纤物理介质依赖（PMD）子层之间的开 - 关控制电路解决了电子电路干扰由IEEE 1394b标准的连接管理协议（CMP）定义的连接检测过程的固有噪声。该电路包括分压器，以提供约50％的输出共模电压的参考电压，电压比较器和耦合到比较器的正输入的反馈以消除可能的振荡。比较器的负输入可以连接到TPB终端网络的中点，并且比较器的正输入可以连接到分压电路的输出。比较器的输出可以连接到光收发器的传输使能条输入。在连接检测过程中，TPB输出的共模电压在0伏和1.5伏之间切换。因此，TPB输出驱动器电路的共模电压的改变将在适当的时间切换光发射机，以满足根据IEEE1394b标准的对等节点处的输入信号定义要求。

7. 发明申请

US20050163457A1 Control circuit for IEEE 1394b optical transmission protocol 失效
标题翻译： IEEE 1394b光传输协议控制电路
公开(公告)号：US20050163457A1
公开(公告)日：2005-07-28
申请号：US10766619
申请日：2004-01-28
申请人： Sam Liu , Yan Wang
发明人： Sam Liu , Yan Wang
IPC分类号： G02B6/00 , H03F3/45
CPC分类号： H03F3/45475
摘要： An On-Off control circuit between the IEEE1394a and IEEE1394b compliant physical layer (PHY) output driver circuitry and the glass fiber optical physical medium dependent (PMD) sub-layer within the architecture of the IEEE 1394b standard addresses the stability issue incurred by electronic circuit's inherent noise that interferes with the connection detecting procedure defined by the connection management protocol (CMP) of the IEEE 1394b standard. The circuit includes of a voltage divider to provide a reference voltage of about 50% of the output common mode voltage, a voltage comparator, and a feedback coupled to the positive input of the comparator to eliminate possible oscillation. The negative input of the comparator may be connected to the mid point of TPB termination network and the positive input of the comparator may be connected to the output of the voltage dividing circuit. The output of the comparator may be connected to the transmission enable bar input of the optical transceiver. In the process of connection detection, the common mode voltage of the TPB output toggles between 0 volt and 1.5 volt. Thus, the changing of the common mode voltage of TPB output driver circuitry will switch the optical transmitter on and off at a proper time to meet with the input signal definition requirements at the peer node according to the IEEE1394b standard.
摘要翻译： IEEE 1394a和IEEE1394b兼容物理层（PHY）输出驱动器电路和IEEE 1394b标准架构内的玻璃光纤物理介质依赖（PMD）子层之间的开 - 关控制电路解决了电子电路干扰由IEEE 1394b标准的连接管理协议（CMP）定义的连接检测过程的固有噪声。该电路包括分压器，以提供约50％的输出共模电压的参考电压，电压比较器和耦合到比较器的正输入的反馈以消除可能的振荡。比较器的负输入可以连接到TPB终端网络的中点，并且比较器的正输入可以连接到分压电路的输出。比较器的输出可以连接到光收发器的传输使能条输入。在连接检测过程中，TPB输出的共模电压在0伏和1.5伏之间切换。因此，TPB输出驱动器电路的共模电压的改变将在适当的时间切换光发射机，以满足根据IEEE1394b标准的对等节点处的输入信号定义要求。

8. 发明授权

US08514938B2 Picture coding apparatus for a still picture sequence and picture decoding apparatus for a still picture sequence 有权
标题翻译：用于静止图像序列的图像编码装置和用于静止图像序列的图像解码装置
公开(公告)号：US08514938B2
公开(公告)日：2013-08-20
申请号：US11576085
申请日：2005-10-05
申请人： Tadamasa Toma , Tomoyuki Okada , Sam Liu
发明人： Tadamasa Toma , Tomoyuki Okada , Sam Liu
IPC分类号： H04N11/02
CPC分类号： H04N19/137 , H04N19/132 , H04N19/159 , H04N19/172 , H04N19/46 , H04N19/70
摘要： A picture coding apparatus reduces a load in decoding. The picture coding apparatus codes each picture according to a picture type of the picture. The picture types include at least an I picture, a P picture, a B picture, and a skipped picture. A first coder is configured to code first supplementary information, including coded pictures and indicating respective picture types of the coded pictures, in a decoding order of the coded pictures. A second coder is configured to code second supplementary information, indicating respective pieces of picture structure information of the coded pictures, in the decoding order. A writer is configured to write, at a position prior to a starting picture, the first supplementary information coded by said first coder and the second supplementary information coded by said second coder.
摘要翻译：图像编码装置减少解码中的负载。图像编码装置根据图像的图像类型对每个图像进行编码。图像类型至少包括I图像，P图像，B图像和跳过的图像。第一编码器被配置为以编码图像的解码顺序对包括编码图像的编码图像和指示编码图像的各个图像类型的第一补充信息进行编码。第二编码器被配置为以解码顺序对第二补充信息进行编码，指示编码图像的各个图像结构信息。写入器被配置为在起始画面之前的位置写入由所述第一编码器编码的第一补充信息和由所述第二编码器编码的第二补充信息。

9. 发明申请

US20090010614A1 Information Storage Medium, Ts Packet Judgement Apparatus, and Data Reproduction Apparatus 失效
标题翻译：信息存储介质，Ts包判定装置和数据再现装置
公开(公告)号：US20090010614A1
公开(公告)日：2009-01-08
申请号：US11575194
申请日：2005-10-05
申请人： Hiroshi Yahata , Tomoyuki Okada , Sam Liu , Gabe B. Beged-Dov
发明人： Hiroshi Yahata , Tomoyuki Okada , Sam Liu , Gabe B. Beged-Dov
IPC分类号： H04N7/00
CPC分类号： G11B27/3027 , G11B20/10527 , G11B27/105
摘要： The present invention provides an information storage medium in which a stream including basic data and extension data for next generation is stored, so as to allow a decoder capable of decoding only basic data to process such a stream including basic data and extension data.Such information storage medium is an information storage medium on which an audio stream including a plurality of TS packets is stored, wherein each of the TS packets includes one of (a) a first packet including basic data, and (b) a second packet including extension data related to the basic data, the basic data is data capable of being decoded into complete sound without requiring the extension data, and the extension data is data intended for improving the quality of audio generated from the basic data, and a header of each of the TS packets includes an identifier indicating whether the TS packet includes the first packet or the second packet.
摘要翻译：本发明提供了一种信息存储介质，其中存储包括用于下一代的基本数据和扩展数据的流，以便允许仅解码基本数据的解码器能够处理包括基本数据和扩展数据的流。这样的信息存储介质是其上存储包括多个TS分组的音频流的信息存储介质，其中每个TS分组包括（a）包括基本数据的第一分组和（b）包括与基本数据相关的扩展数据，基本数据是能够被解码成完整声音而不需要扩展数据的数据，扩展数据是用于提高从基本数据生成的音频的质量的数据，以及每个的TS分组包括指示TS分组是否包括第一分组或第二分组的标识符。

10. 发明申请

US20050281220A1 Systems and methods for implementing double wide channels in a communication system 有权
标题翻译：在通信系统中实现双宽通道的系统和方法
公开(公告)号：US20050281220A1
公开(公告)日：2005-12-22
申请号：US11156045
申请日：2005-06-17
申请人： Kenneth Stanwood , Timothy Gallagher , Sheldon Gilbert , Yair Bourlas , Charles Bergan , Sam Liu , Darren Smith
发明人： Kenneth Stanwood , Timothy Gallagher , Sheldon Gilbert , Yair Bourlas , Charles Bergan , Sam Liu , Darren Smith
IPC分类号： H04H20/77 , H04W28/20 , H04Q7/00
CPC分类号： H04W28/20
摘要： In a system utilizing double wide communication channels, if a particular CPE requires a sustained rate that is greater than the bandwidth of a single channel, data to and from the CPE may be split across Channels A and B. Also, when the bandwidth requirements of a particular CPE peaks at a data rate greater than the capacity of a single channel, the CPE's data may be split across the two channels. In one embodiment, a single-wide CPE may communicate with the base station without knowing that it is communicating with a base station configured to communicate using a double wide channel.
摘要翻译：在使用双宽通信信道的系统中，如果特定的CPE需要比单个信道的带宽更长的持续速率，那么到CPE之间的数据可能会跨越信道A和B分裂。另外，当带宽要求特定的CPE以大于单个信道的容量的数据速率峰值，CPE的数据可以跨越两个信道被分离。在一个实施例中，单宽CPE可以与基站通信，而不知道它正在与被配置为使用双宽信道通信的基站通信。

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