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1. 发明申请

US20140189274A1 APPARATUS AND METHOD FOR PAGE WALK EXTENSION FOR ENHANCED SECURITY CHECKS 有权
标题翻译：用于增强安全检查的页面扩展的装置和方法
公开(公告)号：US20140189274A1
公开(公告)日：2014-07-03
申请号：US13730563
申请日：2012-12-28
申请人： Gur Hildesheim , Ittai Anati , Hisham Shafi , Shlomo Raikin , Gideon Gerzon , Uday R Savagaonkar , Carlos V Rozas , Francis X McKeen , Michael A Goldsmith , Dewan Prashant
发明人： Gur Hildesheim , Ittai Anati , Hisham Shafi , Shlomo Raikin , Gideon Gerzon , Uday R Savagaonkar , Carlos V Rozas , Francis X McKeen , Michael A Goldsmith , Dewan Prashant
IPC分类号： G06F12/14
CPC分类号： G06F12/145 , G06F12/084 , G06F12/1027 , G06F12/1483 , G06F21/53
摘要： An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.
摘要翻译：一种用于由处理器管理保护表的装置和方法。例如，根据本发明的一个实施例的处理器包括：保护表管理逻辑以管理保护表，所述保护表具有用于每个受保护页面的条目或存储器中每组受保护页面; 其中保护表管理逻辑防止用户应用程序代码和操作系统程序代码直接访问保护表，但允许处理器直接访问。

2. 发明授权

US09286235B2 Virtual memory address range register 有权
标题翻译：虚拟内存地址范围寄存器
公开(公告)号：US09286235B2
公开(公告)日：2016-03-15
申请号：US13538900
申请日：2012-06-29
申请人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
发明人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
IPC分类号： G06F9/26 , G06F9/34 , G06F12/10
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口是使用物理内存地址访问系统内存。地址转换硬件是支持将虚拟内存地址转换为物理内存地址。虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

3. 发明申请

US20140006746A1 VIRTUAL MEMORY ADDRESS RANGE REGISTER 有权
标题翻译：虚拟内存地址范围注册
公开(公告)号：US20140006746A1
公开(公告)日：2014-01-02
申请号：US13538900
申请日：2012-06-29
申请人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
发明人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
IPC分类号： G06F12/10
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口是使用物理内存地址访问系统内存。地址转换硬件是支持将虚拟内存地址转换为物理内存地址。虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

4. 发明授权

US09348766B2 Balanced P-LRU tree for a “multiple of 3” number of ways cache 有权
标题翻译：平衡的P-LRU树为“多个3”的缓存方式
公开(公告)号：US09348766B2
公开(公告)日：2016-05-24
申请号：US13994690
申请日：2011-12-21
申请人： Adi Basel , Gur Hildesheim , Shlomo Raikin , Robert Chappell , Ho-Seop Kim , Rohit Bhatia
发明人： Adi Basel , Gur Hildesheim , Shlomo Raikin , Robert Chappell , Ho-Seop Kim , Rohit Bhatia
IPC分类号： G06F13/00 , G06F12/12 , G06F3/06 , G06F12/00 , G06F12/08
CPC分类号： G06F12/122 , G06F3/0604 , G06F12/00 , G06F12/0842 , G06F12/0864 , G06F12/124 , G06F12/125
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a balanced P-LRU tree for a “multiple of 3” number of ways cache. For example, in one embodiment, such means may include an integrated circuit having a cache and a plurality of ways. In such an embodiment the plurality of ways include a quantity that is a multiple of three and not a power of two, and further in which the plurality of ways are organized into a plurality of pairs. In such an embodiment, means further include a single bit for each of the plurality of pairs, in which each single bit is to operate as an intermediate level decision node representing the associated pair of ways and a root level decision node having exactly two individual bits to point to one of the single bits to operate as the intermediate level decision nodes representing an associated pair of ways. In this exemplary embodiment, the total number of bits is N−1, wherein N is the total number of ways in the plurality of ways. Alternative structures are also presented for full LRU implementation, a “multiple of 5” number of cache ways, and variations of the “multiple of 3” number of cache ways.
摘要翻译：根据本文公开的实施例，提供了用于实现用于“3”倍的方式缓存的平衡P-LRU树的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有高速缓存和多个方式的集成电路。在这样的实施例中，多个方式包括量是三的倍数而不是二的幂，并且其中多个方式被组织成多对。在这种实施例中，装置还包括用于多个对中的每一对的单个比特，其中每个单个比特将用作表示相关联的一对路由的中间级别决策节点，以及具有正好两个单独比特的根级别决策节点指向要作为表示相关联的方式的中间级决策节点操作的单个位之一。在该示例性实施例中，总数是N-1，其中N是多个方式的总路数。还提供了替代结构，用于完整的LRU实现，“多路复用5”缓存方式，以及“3”倍数缓存方式的变化。

5. 发明申请

US20140223226A1 APPARATUS AND METHOD FOR DETECTING AND RECOVERING FROM DATA FETCH ERRORS 审中-公开
标题翻译：用于从数据触发错误中检测和恢复的装置和方法
公开(公告)号：US20140223226A1
公开(公告)日：2014-08-07
申请号：US13994609
申请日：2011-12-22
申请人： Theodros Yigzaw , Geeyarpuram N. Santhanakrushnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrushnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
IPC分类号： G06F11/14
CPC分类号： G06F11/1405 , G06F11/1064
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.
摘要翻译：描述了用于检测和校正处理器核心内的数据获取错误的装置和方法。例如，用于检测和从数据获取错误中恢复的指令处理装置的一个实施例包括：具有多个指令处理阶段的至少一个处理器核心，包括数据获取阶段和退休阶段; 以及与处理级通信的错误处理逻辑，以执行以下操作：响应于由数据获取级执行的数据获取操作，检测与数据相关联的错误; 并且响应地执行一个或多个操作以确保该错误不会在退休阶段内破坏处理器核心的体系结构状态。

6. 发明申请

US20140189192A1 APPARATUS AND METHOD FOR A MULTIPLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER (TLB) 审中-公开
标题翻译：多页翻页预处理缓存器（TLB）的设备和方法
公开(公告)号：US20140189192A1
公开(公告)日：2014-07-03
申请号：US13730411
申请日：2012-12-28
申请人： Shlomo Raikin , Oren Hamama , Robert S. Chappell , Camron B. Rust , Han S. Luu , Leslie A. Ong , Gur Hildesheim
发明人： Shlomo Raikin , Oren Hamama , Robert S. Chappell , Camron B. Rust , Han S. Luu , Leslie A. Ong , Gur Hildesheim
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652 , Y02D10/13
摘要： An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.
摘要翻译：一种用于实现多页尺寸翻译后备缓冲器（TLB）的装置和方法。例如，根据一个实施例的方法包括：从线性地址读取第一组位和第二组位; 确定线性地址是否与大页面尺寸或小页面尺寸相关联; 如果所述线性地址与第一页面尺寸相关联，则使用所述第一组位标识第一高速缓存集合，并且如果所述线性地址与第二页面尺寸相关联则使用所述第二组位标识第二高速缓存集合; 以及如果所述线性地址与第一页面尺寸相关联并且如果所述线性地址与第二页面尺寸相关联则识别第二高速缓存路线，则识别第一高速缓存路线。

7. 发明授权

US10223204B2 Apparatus and method for detecting and recovering from data fetch errors 有权
公开(公告)号：US10223204B2
公开(公告)日：2019-03-05
申请号：US13994609
申请日：2011-12-22
申请人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
IPC分类号： G06F11/00 , G06F11/14 , G06F11/10
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

8. 发明授权

US09626333B2 Scatter using index array and finite state machine 有权
公开(公告)号：US09626333B2
公开(公告)日：2017-04-18
申请号：US13977727
申请日：2012-06-02
申请人： Zeev Sperber , Robert Valentine , Shlomo Raikin , Stanislav Shwartsman , Gal Ofir , Igor Yanover , Guy Patkin , Levy Ofer
发明人： Zeev Sperber , Robert Valentine , Shlomo Raikin , Stanislav Shwartsman , Gal Ofir , Igor Yanover , Guy Patkin , Levy Ofer
IPC分类号： G06F9/00 , G06F15/78 , G06F9/30 , G06F9/345 , G06F9/38
CPC分类号： G06F15/7839 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3808 , G06F9/383
摘要： Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

9. 发明授权

US09268697B2 Snoop filter having centralized translation circuitry and shadow tag array 有权
标题翻译：具有集中翻译电路和阴影标签阵列的窥探滤波器
公开(公告)号：US09268697B2
公开(公告)日：2016-02-23
申请号：US13730956
申请日：2012-12-29
申请人： Ilan Pardo , Niranjan Cooray , Stanislav Shwartsman , Shlomo Raikin
发明人： Ilan Pardo , Niranjan Cooray , Stanislav Shwartsman , Shlomo Raikin
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0822 , G06F12/0831 , G06F12/1027 , G06F12/1063
摘要： A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.
摘要翻译：描述了包括多个处理核的处理器。处理器包括耦合到每个所述处理核心的互连网络。处理器包括连接到互连网络并与处理器的相干平面逻辑电路相关联的窥探滤波器逻辑电路。监听滤波器逻辑电路包含用于保存信息的电路，该信息不仅识别哪个处理核心缓存由处理核心高速缓存的特定高速缓存线，而且在处理核心的高速缓存中缓存高速缓存行被缓存。

10. 发明授权

US08914617B2 Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register 有权
标题翻译：跟踪机制耦合到重排序缓冲器中，用于指示由逻辑寄存器索引的记录中的物理寄存器的共享逻辑寄存器
公开(公告)号：US08914617B2
公开(公告)日：2014-12-16
申请号：US12978513
申请日：2010-12-24
申请人： Shlomo Raikin , David J. Sager , Zeev Sperber , Evgeni Krimer , Ori Lempel , Stanislav Shwartsman , Adi Yoaz , Omer Golz
发明人： Shlomo Raikin , David J. Sager , Zeev Sperber , Evgeni Krimer , Ori Lempel , Stanislav Shwartsman , Adi Yoaz , Omer Golz
IPC分类号： G06F9/34 , G06F12/08 , G06F9/38
CPC分类号： G06F12/0862 , G06F9/30032 , G06F9/3824 , G06F9/384 , Y02D10/13
摘要： Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.
摘要翻译：描述与硬件移动消除和/或下一页预取相关的方法和装置。在一些实施例中，逻辑可以基于存储的数据提供硬件移动消除。在一个实施例中，公开了下一页预取器。还描述和要求保护其他实施例。

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