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1. 发明授权

US07884675B2 Phase locked loop including a frequency change module 有权
标题翻译：锁相环包括变频模块
公开(公告)号：US07884675B2
公开(公告)日：2011-02-08
申请号：US12318906
申请日：2009-01-12
申请人： Hung-Ming Chien
发明人： Hung-Ming Chien
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L7/0891 , H03L7/18 , H03L7/23
摘要： A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.
摘要翻译：锁相环（PLL）包括检测器，电荷泵，环路滤波器，压控振荡器（VCO），分频器和频率改变模块。检测器基于参考信号和反馈信号提供相位差。电荷泵基于相位差提供电荷。环路滤波器基于电荷提供电压。 VCO基于从环路滤波器接收的电压提供输出信号。分频器将输出信号的频率除以一个值，以提供反馈信号。频率变化模块处理具有第一频率的输入信号以提供具有不同于第一频率的第二频率的处理信号。频率变化模块选择输入信号或处理后的信号作为参考信号提供给检测器。更改参考信号的频率可能会改变频率。

2. 发明授权

US07834707B2 Linearized charge pump having an offset 失效
标题翻译：具有偏移的线性化电荷泵
公开(公告)号：US07834707B2
公开(公告)日：2010-11-16
申请号：US11314331
申请日：2005-12-22
申请人： Hung-Ming Chien
发明人： Hung-Ming Chien
IPC分类号： H03L7/085
CPC分类号： H03L7/0895 , H03L7/1976
摘要： A charge pump provides charge based on a phase difference between a reference signal and a feedback signal. The relationship between the charge and the phase difference is referred to as the charge phase relationship. Charge pumps typically have a non-linear charge phase relationship. A non-linear portion of the charge phase relationship occurs about a point at which the charge and the phase difference are substantially zero. Points along charge phase relationship that represent the performance of charge pump are referred to as the charge phase characteristic of the charge pump. The charge pump includes an offset current circuit, which biases the charge pump to have a linear charge phase characteristic. For example, the charge pump is biased to have a charge phase characteristic that does not overlap with the non-linear portion of the charge phase relationship.
摘要翻译：电荷泵基于参考信号和反馈信号之间的相位差来提供电荷。电荷与相位差之间的关系称为电荷相位关系。电荷泵通常具有非线性电荷相位关系。充电相位关系的非线性部分发生在电荷和相位差基本上为零的点处。表示电荷泵性能的电荷相位关系的点被称为电荷泵的充电相位特性。电荷泵包括偏置电流电路，其偏置电荷泵以具有线性电荷相位特性。例如，电荷泵偏置为具有不与充电相位关系的非线性部分重叠的电荷相位特性。

3. 发明授权

US07242256B2 Phase frequency detector with programmable delay 有权
标题翻译：具有可编程延迟的相位频率检测器
公开(公告)号：US07242256B2
公开(公告)日：2007-07-10
申请号：US11084335
申请日：2005-03-18
申请人： Hung-Ming Chien
发明人： Hung-Ming Chien
IPC分类号： H03L7/00
CPC分类号： H03L7/089 , H03D13/004 , H03L7/081 , H03L7/0891
摘要： Methods and systems for locking a phase locked loop (PLL) are disclosed herein. A first impulse signal may be generated utilizing an input reference signal. A second impulse signal may be generated utilizing an input divided signal. A programmable delay signal may be generated based on the generated first impulse signal and the generated second impulse signal. The generation of the first impulse signal and the generation of the second impulse signal may be controlled via the generated programmable delay signal. The generated first impulse signal and the generated second impulse signal may be delayed utilizing a programmable delay. The delayed first impulse signal and the delayed second impulse signal may be ANDed to generate the programmable delay signal, and the generated programmable delay signal may comprise a reset signal.
摘要翻译：本文公开了用于锁定锁相环（PLL）的方法和系统。可以利用输入参考信号来产生第一脉冲信号。可以利用输入的分频信号产生第二脉冲信号。可以基于所生成的第一脉冲信号和所生成的第二脉冲信号来生成可编程延迟信号。可以经由所生成的可编程延迟信号来控制第一脉冲信号的产生和第二脉冲信号的产生。所产生的第一脉冲信号和产生的第二脉冲信号可以使用可编程延迟来延迟。延迟的第一脉冲信号和延迟的第二脉冲信号可以进行与运算以产生可编程延迟信号，并且生成的可编程延迟信号可以包括复位信号。

4. 发明申请

US20070069329A1 Apparatus and method for reducing parasitic capacitance in a semiconductor device 有权
标题翻译：用于减小半导体器件中的寄生电容的装置和方法
公开(公告)号：US20070069329A1
公开(公告)日：2007-03-29
申请号：US11320471
申请日：2005-12-29
申请人： Hung-Ming Chien
发明人： Hung-Ming Chien
IPC分类号： H01L29/00
CPC分类号： H03B5/1228 , H03B5/1212 , H03B5/1265
摘要： A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third substrate is formed on the second substrate; and the metal element is formed on the third substrate. The second substrate is electrically grounded and is highly doped with acceptor dopant as compared to the first substrate. In this way, the second resistivity is lower than the first resistivity.
摘要翻译：具有低寄生电阻的半导体器件包括以第一电阻率为特征的第一衬底; 第二基板，其特征在于第二电阻率，第三基板和金属元件。这些衬底形成多层半导体器件，其中第二衬底形成在第一衬底上; 所述第三基板形成在所述第二基板上; 并且金属元件形成在第三基板上。与第一衬底相比，第二衬底电接地并且与受体掺杂物高度掺杂。以这种方式，第二电阻率低于第一电阻率。

5. 发明授权

US07196559B2 Multi-modulus divider for high speed applications 失效
标题翻译：用于高速应用的多模式分压器
公开(公告)号：US07196559B2
公开(公告)日：2007-03-27
申请号：US11084945
申请日：2005-03-21
申请人： Hung-Ming Chien
发明人： Hung-Ming Chien
IPC分类号： H03K21/00
CPC分类号： H03L7/193 , H03K23/667
摘要： A multi-modulus divider for high speed applications is provided and may comprise a multistage divider generating a divided signal from an output portion of a divider module for a current stage. The divided signal may be fed back to an input portion of the divider module in the current stage via a reduced feedback delay path. If the input portion of the divider module in the current stage is coupled to the divider module in a previous stage, a first load signal may be communicated from the divider module in the current stage to the divider module in the previous stage. If the divider module in the current stage is coupled to the divider module in the previous stage, the method may further comprise receiving the divided signal from the divider module in the previous stage.
摘要翻译：提供了用于高速应用的多模式分频器，并且可以包括多级分频器，用于产生来自用于当前级的分频器模块的输出部分的分频信号。分频信号可以经由减小的反馈延迟路径反馈到当前级中的分频器模块的输入部分。如果当前阶段中的分频器模块的输入部分在前一级耦合到分频器模块，那么可以将第一负载信号从当前级的分频器模块传送到前一级的分频器模块。如果当前级中的分频器模块在前一级耦合到分频器模块，则该方法还可以包括在前一级从分频器模块接收分频信号。

6. 发明申请

US20060271818A1 Data storage system and managing method thereof 有权
标题翻译：数据存储系统及其管理方法
公开(公告)号：US20060271818A1
公开(公告)日：2006-11-30
申请号：US11319664
申请日：2005-12-29
申请人： Hung-Ming Chien
发明人： Hung-Ming Chien
IPC分类号： G06F11/00
CPC分类号： G06F11/2094 , G06F11/076 , G06F11/1662
摘要： A method for managing a data storage system is provided. The data storage system includes a primary storage device and a spare storage device. The primary storage device includes a plurality of sections. The method first judges whether the primary storage device conforms to a first standard. Once the judging result is NO, the primary storage device is replaced with the spare storage device. The method then scans the primary storage device, checks which sections are failed in the primary storage device, and locates the failed sections. Then, the method repairs the failed sections that can be repaired and judges whether the primary storage device conforms to a second standard. If the primary storage device conforms to the second standard, the method sets the primary storage device as a new spare storage device.
摘要翻译：提供了一种用于管理数据存储系统的方法。数据存储系统包括主存储设备和备用存储设备。主存储装置包括多个部分。该方法首先判断主存储装置是否符合第一标准。一旦判断结果为“否”，则主存储设备被替换为备用存储设备。然后，该方法扫描主存储设备，检查主存储设备中哪些部分故障，并找到故障部分。然后，该方法修复可以修复的故障部分，并判断主存储设备是否符合第二标准。如果主存储设备符合第二标准，则该方法将主存储设备设置为新的备用存储设备。

7. 发明申请

US20060077014A1 Oscillator with quadrature output in a cross-coupled configuration 有权
标题翻译：具有交叉耦合配置的正交输出的振荡器
公开(公告)号：US20060077014A1
公开(公告)日：2006-04-13
申请号：US11226435
申请日：2005-09-15
申请人： Hung-Ming Chien
发明人： Hung-Ming Chien
IPC分类号： H03B5/20
CPC分类号： H03B5/20 , H03B27/00
摘要： An oscillator that provides a quadrature output and has a cross-coupled configuration is disclosed. The oscillator generates an output signal having a frequency. Two phase shift circuits, or stages, are activated by a control signal to provide phase shifts within the oscillator. Each phase shift circuit includes poles to provide the phase shift. A pole includes a varactor to tune, adjust or vary the phase shift accordingly,
摘要翻译：公开了提供正交输出并具有交叉耦合配置的振荡器。振荡器产生具有频率的输出信号。两个相移电路或级由控制信号激活，以提供振荡器内的相移。每个相移电路包括提供相移的极点。极点包括相应调整，调整或改变相移的变容二极管，

8. 发明申请

US20060057992A1 Frequency allocation using a single VCO 有权
标题翻译：使用单个VCO进行频率分配
公开(公告)号：US20060057992A1
公开(公告)日：2006-03-16
申请号：US11060325
申请日：2005-02-17
申请人： Hung-Ming Chien , Keith Carter
发明人： Hung-Ming Chien , Keith Carter
IPC分类号： H04B7/00 , H04B1/06
CPC分类号： H03L7/183 , H04B1/0082
摘要： An apparatus and method to use a single voltage controlled oscillator (VCO) to generate frequencies to cover multiple frequency bands. The single VCO generates local oscillator signals for more than one frequency band of a communication standard or protocol, such as the IEEE 802.11 standard.
摘要翻译：一种使用单个压控振荡器（VCO）产生频率以覆盖多个频带的装置和方法。单个VCO为诸如IEEE 802.11标准的通信标准或协议的多于一个频带产生本地振荡器信号。

9. 发明申请

US20060035597A1 Linearized fractional-N synthesizer having a gated offset 有权
$Linearized fractional-N synthesizer having a gated offset$
公开(公告)号：US20060035597A1
公开(公告)日：2006-02-16
申请号：US11222632
申请日：2005-09-09
申请人： Tsung-Hsien Lin , Hung-Ming Chien
发明人： Tsung-Hsien Lin , Hung-Ming Chien
IPC分类号： H04B1/40 , H04B7/00
CPC分类号： H03L7/1976 , H03L7/0891 , H04W84/042 , H04W84/18 , H04W88/02
摘要： A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

10. 发明授权

US06985708B2 Linearized fractional-N synthesizer having a gated offset 有权
$Linearized fractional-N synthesizer having a gated offset$
公开(公告)号：US06985708B2
公开(公告)日：2006-01-10
申请号：US10170849
申请日：2002-06-12
申请人： Tsung-Hsien Lin , Hung-Ming Chien
发明人： Tsung-Hsien Lin , Hung-Ming Chien
IPC分类号： H04B1/06
CPC分类号： H03L7/1976 , H03L7/0891 , H04W84/042 , H04W84/18 , H04W88/02
摘要： A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

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