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1. 发明授权

US06815296B2 Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control 有权
标题翻译：多晶硅背栅SOI MOSFET用于动态阈值电压控制
公开(公告)号：US06815296B2
公开(公告)日：2004-11-09
申请号：US10659950
申请日：2003-09-11
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L29/41783 , H01L29/458 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法。 SOI MOSFET器件包括多晶硅背栅极，其控制含多晶硅的前栅极的阈值电压。背栅极作为SOI MOSFET器件中的动态阈值电压控制系统起作用，因为它适用于电路/系统有效期间和电路/系统空闲期间。

2. 发明授权

US06664598B1 Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control 有权
标题翻译：多晶硅背栅SOI MOSFET用于动态阈值电压控制
公开(公告)号：US06664598B1
公开(公告)日：2003-12-16
申请号：US10235169
申请日：2002-09-05
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L29/41783 , H01L29/458 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法。 SOI MOSFET器件包括多晶硅背栅极，其控制含多晶硅的前栅极的阈值电压。背栅极作为SOI MOSFET器件中的动态阈值电压控制系统起作用，因为它适用于电路/系统有效期间和电路/系统空闲期间。

3. 发明授权

US06812527B2 Method to control device threshold of SOI MOSFET's 有权
标题翻译：控制SOI MOSFET器件阈值的方法
公开(公告)号：US06812527B2
公开(公告)日：2004-11-02
申请号：US10235147
申请日：2002-09-05
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/78621 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其中注入的背栅极形成为SOI晶片的含Si层。如此形成的注入后栅极能够控制在植入的背栅区域的一部分上形成的含多晶硅的前栅的阈值电压。在SOI MOSFET器件中，植入式背栅可用作动态阈值电压控制系统，因为它适用于电路/系统有效期间和电路/系统空闲期间。

4. 发明授权

US07273785B2 Method to control device threshold of SOI MOSFET's 失效
标题翻译：控制SOI MOSFET器件阈值的方法
公开(公告)号：US07273785B2
公开(公告)日：2007-09-25
申请号：US10965992
申请日：2004-10-15
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/78621 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其中注入的背栅极形成为SOI晶片的含Si层。如此形成的注入后栅极能够控制在植入的背栅区域的一部分上形成的含多晶硅的前栅的阈值电压。在SOI MOSFET器件中，植入式背栅可用作动态阈值电压控制系统，因为它适用于电路/系统有效期间和电路/系统空闲期间。

5. 发明授权

US07089515B2 Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power 有权
标题翻译：使用后门控MOSFET器件进行阈值电压滚降补偿，用于系统高性能和低待机功耗
公开(公告)号：US07089515B2
公开(公告)日：2006-08-08
申请号：US10796805
申请日：2004-03-09
申请人： Hussein I. Hanafi , Robert H. Dennard , Wilfried E. Haensch
发明人： Hussein I. Hanafi , Robert H. Dennard , Wilfried E. Haensch
IPC分类号： G06F17/50
CPC分类号： H03K19/0013
摘要： A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For the present invention, it is assumed that the channel length of these transistors at the completion of chip manufacturing is Lmax. This enables one to set the off-current to the maximum value of I-offmax which is done by setting the threshold voltage value to Vtmin. The Vtmin for these transistors is obtained during processing by using the proper implant dose. After manufacturing, the transistors are then tested to determine the off-current thereof. Some transistors within the system or chip will have an off-current value that meets a current specification. For those transistor devices, no further compensation is required. For other transistors within the system or chip, the off-current is not within the predetermined specification. For those transistors, threshold voltage roll-off has occurred since they are transistors that have a channel length that is less than nominal. For such short channel transistors, the threshold voltage is low, even lower than Vtmin, and the off-current is high, even higher than I-offmax. Compensation of the short channel transistors is achieved in the present invention by biasing the back-gate or body node to give increased threshold voltage about equal to Vtmin and hence an off-current that meets the predetermined specification, which is about equal to I-offmax.
摘要翻译：提供了使用包含背栅或体节点的晶体管补偿阈值电压滚降的方法。该方法包括设计具有通道长度为L nom的多个晶体管的半导体系统或芯片。对于本发明，假设在芯片制造完成时这些晶体管的沟道长度为L max max。这使得能够将截止电流设置为通过将阈值电压值设置为Vt分钟来完成的I-OFF 的最大值。通过使用适当的植入剂量，在处理期间获得这些晶体管的Vt 。在制造之后，然后测试晶体管以确定其截止电流。系统或芯片内的一些晶体管将具有满足当前规范的截止值。对于那些晶体管器件，不需要进一步的补偿。对于系统或芯片内的其他晶体管，截止电流不在预定的规范内。对于那些晶体管，已经发生阈值电压滚降，因为它们是具有小于额定值的沟道长度的晶体管。对于这种短沟道晶体管，阈值电压低，甚至低于Vt分钟<！ - SIPO - >，并且截止电流高，甚至高于I-off最大值。在本发明中通过偏置背栅极或体节点以提供大约等于Vt分钟的阈值电压，从而达到满足预定规格的截止电流来实现短沟道晶体管的补偿，其大约等于I-off最大。

6. 发明授权

US07018873B2 Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate 失效
标题翻译：使用自对准后栅极对前栅极绝缘体上硅MOSFET进行器件阈值控制的方法
公开(公告)号：US07018873B2
公开(公告)日：2006-03-28
申请号：US10639942
申请日：2003-08-13
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L21/76256 , H01L21/76275 , H01L29/66772 , H01L29/78648 , H01L29/78654
摘要： provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.
摘要翻译：提供SOI CMOS技术，由此使用多晶硅背栅极来控制前栅极器件的阈值电压，并且nMOS和pMOS背栅源彼此独立地切换和前栅极。具体地说，本发明提供了一种制造背栅绝缘的CMOS器件的方法，其中器件的背栅与器件的前栅极以及源极/漏极延伸部分自对准。这种结构使电容最小化，同时增强了器件和电路性能。使用现有的SIMOX（通过离子注入氧气的分离）或结合的SOI晶片结合和减薄，多晶硅蚀刻，低压化学气相沉积和化学机械抛光来制造本发明的背栅完全耗尽的CMOS器件。

7. 发明授权

US5206544A CMOS off-chip driver with reduced signal swing and reduced power supply disturbance 失效
标题翻译： CMOS片外驱动器具有降低的信号摆幅和减少电源干扰
公开(公告)号：US5206544A
公开(公告)日：1993-04-27
申请号：US682753
申请日：1991-04-08
申请人： Chih-Liang Chen , Robert H. Dennard , Hussein I. Hanafi
发明人： Chih-Liang Chen , Robert H. Dennard , Hussein I. Hanafi
IPC分类号： H03K17/00 , H03K17/16 , H03K17/687 , H03K19/0175
CPC分类号： H03K17/163 , H03K2217/0036
摘要： An off-chip driver circuit which includes a complementary pair of field effect transistor source followers connected in a non-inverting series circuit arrangement. The driver circuit includes an n-channel device to pull the output up to the positive supply less the threshold drop across the device and a p-channel device to pull the output down for the opposite transition to within a threshold voltage drop above ground of the p-channel device. The driver circuit includes means for eliminating body effect by connecting the n(p)-well of the p(n) channel transistor to the output node. The driver circuit provides a reduced swing low noise output which reduces the collapse of the power supply. The driver circuit provides an appropriate impedance match to the output transmission line, so that the output transmission line can be terminated to eliminate reflections.
摘要翻译：片外驱动电路，其包括以非反相串联电路布置连接的互补的一对场效应晶体管源极跟随器。驱动器电路包括n沟道器件，用于将输出拉至正电源，减去器件上的阈值下降，以及p沟道器件，以将输出向下拉，用于相反的转变，使之达到在 p通道设备。驱动器电路包括通过将p（n）沟道晶体管的n（p）阱连接到输出节点来消除体效应的装置。驱动器电路提供降低的摆幅低噪声输出，减少电源的崩溃。驱动电路为输出传输线提供适当的阻抗匹配，从而可以终止输出传输线，以消除反射。

8. 发明申请

US20120313216A1 COMPLEMENTARY BIPOLAR INVERTER 有权
标题翻译：补充双极反相器
公开(公告)号：US20120313216A1
公开(公告)日：2012-12-13
申请号：US13158419
申请日：2011-06-12
申请人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L27/082 , H01L21/8228
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

9. 发明授权

US07838942B2 Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
标题翻译：用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案
公开(公告)号：US07838942B2
公开(公告)日：2010-11-23
申请号：US12144272
申请日：2008-06-23
申请人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
发明人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
IPC分类号： H01L29/76
CPC分类号： H01L27/1108
摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.
摘要翻译：一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂提供了特定的水平，以提高不同器件区域内的FET器件的性能。特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

10. 发明申请

US20080258221A1 SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES 有权
标题翻译：用于具有共同逻辑设备的后盖控制SRAM的基板解决方案
公开(公告)号：US20080258221A1
公开(公告)日：2008-10-23
申请号：US12144272
申请日：2008-06-23
申请人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
发明人： Robert H. Dennard , Wilfried E. Haensch , Arvind Kumar , Robert J. Miller
IPC分类号： H01L27/11
CPC分类号： H01L27/1108
摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.
摘要翻译：一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂提供了特定的水平，以提高不同器件区域内的FET器件的性能。特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

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