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1. 发明授权

US06664598B1 Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control 有权
标题翻译：多晶硅背栅SOI MOSFET用于动态阈值电压控制
公开(公告)号：US06664598B1
公开(公告)日：2003-12-16
申请号：US10235169
申请日：2002-09-05
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L29/41783 , H01L29/458 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法。 SOI MOSFET器件包括多晶硅背栅极，其控制含多晶硅的前栅极的阈值电压。背栅极作为SOI MOSFET器件中的动态阈值电压控制系统起作用，因为它适用于电路/系统有效期间和电路/系统空闲期间。

2. 发明授权

US06815296B2 Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control 有权
标题翻译：多晶硅背栅SOI MOSFET用于动态阈值电压控制
公开(公告)号：US06815296B2
公开(公告)日：2004-11-09
申请号：US10659950
申请日：2003-09-11
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L29/41783 , H01L29/458 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided. The SOI MOSFET device includes a polysilicon back-gate which controls the threshold voltage of a polysilicon-containing front-gate. The back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法。 SOI MOSFET器件包括多晶硅背栅极，其控制含多晶硅的前栅极的阈值电压。背栅极作为SOI MOSFET器件中的动态阈值电压控制系统起作用，因为它适用于电路/系统有效期间和电路/系统空闲期间。

3. 发明授权

US06812527B2 Method to control device threshold of SOI MOSFET's 有权
标题翻译：控制SOI MOSFET器件阈值的方法
公开(公告)号：US06812527B2
公开(公告)日：2004-11-02
申请号：US10235147
申请日：2002-09-05
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/78621 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其中注入的背栅极形成为SOI晶片的含Si层。如此形成的注入后栅极能够控制在植入的背栅区域的一部分上形成的含多晶硅的前栅的阈值电压。在SOI MOSFET器件中，植入式背栅可用作动态阈值电压控制系统，因为它适用于电路/系统有效期间和电路/系统空闲期间。

4. 发明授权

US07273785B2 Method to control device threshold of SOI MOSFET's 失效
标题翻译：控制SOI MOSFET器件阈值的方法
公开(公告)号：US07273785B2
公开(公告)日：2007-09-25
申请号：US10965992
申请日：2004-10-15
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L29/66772 , H01L29/458 , H01L29/78621 , H01L29/78648
摘要： A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.
摘要翻译：提供了一种形成绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）器件的方法，其中注入的背栅极形成为SOI晶片的含Si层。如此形成的注入后栅极能够控制在植入的背栅区域的一部分上形成的含多晶硅的前栅的阈值电压。在SOI MOSFET器件中，植入式背栅可用作动态阈值电压控制系统，因为它适用于电路/系统有效期间和电路/系统空闲期间。

5. 发明授权

US07089515B2 Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power 有权
标题翻译：使用后门控MOSFET器件进行阈值电压滚降补偿，用于系统高性能和低待机功耗
公开(公告)号：US07089515B2
公开(公告)日：2006-08-08
申请号：US10796805
申请日：2004-03-09
申请人： Hussein I. Hanafi , Robert H. Dennard , Wilfried E. Haensch
发明人： Hussein I. Hanafi , Robert H. Dennard , Wilfried E. Haensch
IPC分类号： G06F17/50
CPC分类号： H03K19/0013
摘要： A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For the present invention, it is assumed that the channel length of these transistors at the completion of chip manufacturing is Lmax. This enables one to set the off-current to the maximum value of I-offmax which is done by setting the threshold voltage value to Vtmin. The Vtmin for these transistors is obtained during processing by using the proper implant dose. After manufacturing, the transistors are then tested to determine the off-current thereof. Some transistors within the system or chip will have an off-current value that meets a current specification. For those transistor devices, no further compensation is required. For other transistors within the system or chip, the off-current is not within the predetermined specification. For those transistors, threshold voltage roll-off has occurred since they are transistors that have a channel length that is less than nominal. For such short channel transistors, the threshold voltage is low, even lower than Vtmin, and the off-current is high, even higher than I-offmax. Compensation of the short channel transistors is achieved in the present invention by biasing the back-gate or body node to give increased threshold voltage about equal to Vtmin and hence an off-current that meets the predetermined specification, which is about equal to I-offmax.
摘要翻译：提供了使用包含背栅或体节点的晶体管补偿阈值电压滚降的方法。该方法包括设计具有通道长度为L nom的多个晶体管的半导体系统或芯片。对于本发明，假设在芯片制造完成时这些晶体管的沟道长度为L max max。这使得能够将截止电流设置为通过将阈值电压值设置为Vt分钟来完成的I-OFF 的最大值。通过使用适当的植入剂量，在处理期间获得这些晶体管的Vt 。在制造之后，然后测试晶体管以确定其截止电流。系统或芯片内的一些晶体管将具有满足当前规范的截止值。对于那些晶体管器件，不需要进一步的补偿。对于系统或芯片内的其他晶体管，截止电流不在预定的规范内。对于那些晶体管，已经发生阈值电压滚降，因为它们是具有小于额定值的沟道长度的晶体管。对于这种短沟道晶体管，阈值电压低，甚至低于Vt分钟<！ - SIPO - >，并且截止电流高，甚至高于I-off最大值。在本发明中通过偏置背栅极或体节点以提供大约等于Vt分钟的阈值电压，从而达到满足预定规格的截止电流来实现短沟道晶体管的补偿，其大约等于I-off最大。

6. 发明授权

US07018873B2 Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate 失效
标题翻译：使用自对准后栅极对前栅极绝缘体上硅MOSFET进行器件阈值控制的方法
公开(公告)号：US07018873B2
公开(公告)日：2006-03-28
申请号：US10639942
申请日：2003-08-13
申请人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
发明人： Robert H. Dennard , Wilfried E. Haensch , Hussein I. Hanafi
IPC分类号： H01L21/00
CPC分类号： H01L29/78696 , H01L21/76256 , H01L21/76275 , H01L29/66772 , H01L29/78648 , H01L29/78654
摘要： provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.
摘要翻译：提供SOI CMOS技术，由此使用多晶硅背栅极来控制前栅极器件的阈值电压，并且nMOS和pMOS背栅源彼此独立地切换和前栅极。具体地说，本发明提供了一种制造背栅绝缘的CMOS器件的方法，其中器件的背栅与器件的前栅极以及源极/漏极延伸部分自对准。这种结构使电容最小化，同时增强了器件和电路性能。使用现有的SIMOX（通过离子注入氧气的分离）或结合的SOI晶片结合和减薄，多晶硅蚀刻，低压化学气相沉积和化学机械抛光来制造本发明的背栅完全耗尽的CMOS器件。

7. 发明授权

US5206544A CMOS off-chip driver with reduced signal swing and reduced power supply disturbance 失效
标题翻译： CMOS片外驱动器具有降低的信号摆幅和减少电源干扰
公开(公告)号：US5206544A
公开(公告)日：1993-04-27
申请号：US682753
申请日：1991-04-08
申请人： Chih-Liang Chen , Robert H. Dennard , Hussein I. Hanafi
发明人： Chih-Liang Chen , Robert H. Dennard , Hussein I. Hanafi
IPC分类号： H03K17/00 , H03K17/16 , H03K17/687 , H03K19/0175
CPC分类号： H03K17/163 , H03K2217/0036
摘要： An off-chip driver circuit which includes a complementary pair of field effect transistor source followers connected in a non-inverting series circuit arrangement. The driver circuit includes an n-channel device to pull the output up to the positive supply less the threshold drop across the device and a p-channel device to pull the output down for the opposite transition to within a threshold voltage drop above ground of the p-channel device. The driver circuit includes means for eliminating body effect by connecting the n(p)-well of the p(n) channel transistor to the output node. The driver circuit provides a reduced swing low noise output which reduces the collapse of the power supply. The driver circuit provides an appropriate impedance match to the output transmission line, so that the output transmission line can be terminated to eliminate reflections.
摘要翻译：片外驱动电路，其包括以非反相串联电路布置连接的互补的一对场效应晶体管源极跟随器。驱动器电路包括n沟道器件，用于将输出拉至正电源，减去器件上的阈值下降，以及p沟道器件，以将输出向下拉，用于相反的转变，使之达到在 p通道设备。驱动器电路包括通过将p（n）沟道晶体管的n（p）阱连接到输出节点来消除体效应的装置。驱动器电路提供降低的摆幅低噪声输出，减少电源的崩溃。驱动电路为输出传输线提供适当的阻抗匹配，从而可以终止输出传输线，以消除反射。

8. 发明授权

US07934181B2 Method and apparatus for improving SRAM cell stability by using boosted word lines 有权
标题翻译：通过使用升压字线来提高SRAM单元稳定性的方法和装置
公开(公告)号：US07934181B2
公开(公告)日：2011-04-26
申请号：US12130472
申请日：2008-05-30
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： G06F17/50 , G11C16/06 , G11C7/00 , G11C8/00
CPC分类号： G11C7/02 , G11C8/08 , G11C11/413
摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要翻译：本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高以将细胞稳定性提高到所需水平。具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

9. 发明申请

US20100188889A1 BACK GATED SRAM CELL 有权
公开(公告)号：US20100188889A1
公开(公告)日：2010-07-29
申请号：US12752286
申请日：2010-04-01
申请人： Hussein I. Hanafi
发明人： Hussein I. Hanafi
IPC分类号： G11C11/00
CPC分类号： H01L27/1108 , G11C11/412 , G11C11/413 , H01L29/785
摘要： Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a write operation. The method includes applying a ground to the back gate of the pair of cross coupled p-type pull up transistors during a read operation. The charge stored on a pair of cross coupled storage nodes of the SRAM is coupled to a front gate and a back gate of a pair of cross coupled n-type pull down transistors in the SRAM during the write operation and during a read operation.
摘要翻译：提供了用于后门控静态随机存取存储器（SRAM）单元的方法，装置和系统。用于操作SRAM单元的一个方法实施例包括在写入操作期间将电位施加到SRAM中的一对交叉耦合p型上拉晶体管的背栅极。该方法包括在读取操作期间将接地施加到该对交叉耦合p型上拉晶体管的背栅极。存储在SRAM的一对交叉耦合的存储节点上的电荷在写入操作期间和在读取操作期间耦合到SRAM中的一对交叉耦合的n型下拉晶体管的前栅极和后栅极。

10. 发明授权

US07732286B2 Buried biasing wells in FETs (Field Effect Transistors) 有权
标题翻译： FET中的埋置偏置阱（场效应晶体管）
公开(公告)号：US07732286B2
公开(公告)日：2010-06-08
申请号：US11845244
申请日：2007-08-27
申请人： Hussein I. Hanafi , Edward J. Nowak
发明人： Hussein I. Hanafi , Edward J. Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/105 , H01L29/0653 , H01L29/66628 , H01L29/7834
摘要： A method for fabricating a semiconductor structure. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in physical contact with the channel region; and a buried barrier region being disposed between the buried well region and the first source/drain region and being disposed between the buried well region and the second source/drain region, wherein the buried barrier region is adapted for preventing current leakage and dopant diffusion between the buried well region and the first source/drain region and between the buried well region and the second source/drain region.
摘要翻译：一种半导体结构的制造方法。半导体结构包括第一和第二源极/漏极区域; 设置在所述第一和第二源极/漏极区之间的沟道区; 与通道区域物理接触的掩埋阱区域; 并且埋置的阻挡区域设置在所述掩埋阱区域和所述第一源极/漏极区域之间并且设置在所述掩埋阱区域和所述第二源极/漏极区域之间，其中所述掩埋势垒区域适于防止所述掩埋阻挡区域之间的电流泄漏和掺杂剂扩散埋入阱区域和第一源极/漏极区域以及掩埋阱区域和第二源极/漏极区域之间。

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