专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110148684A1 SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：连续逼近模拟数字转换器
公开(公告)号：US20110148684A1
公开(公告)日：2011-06-23
申请号：US12970861
申请日：2010-12-16
申请人： Hyun Kyu Yu , Seon Ho Han , Young Hwa Kim , Seong Hwan Cho
发明人： Hyun Kyu Yu , Seon Ho Han , Young Hwa Kim , Seong Hwan Cho
IPC分类号： H03M1/38
CPC分类号： H03M1/46 , H03M1/827
摘要： There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code.
摘要翻译：提供了仅包括最小电容器以执行模数转换操作的逐次逼近模数转换器，从而使得可以具有非常强的工艺变化电阻特性，同时具有减小的电容和电路面积。逐次逼近模数转换器可以包括提供参考电流的参考电流提供单元; 信号存储单元，存储通过对参考电流进行充电而产生的参考信号和从外部输入的输入信号; 比较单元，其比较所述参考信号和所述输入信号; 以及控制器，其基于所述比较单元的比较结果来控制所述参考电流供给单元，同时根据所述二进制码来改变提供给所述信号存储单元的参考电流的供给量。

2. 发明授权

US08274420B2 Successive approximation analog-to-digital converter 有权
标题翻译：逐次近似模数转换器
公开(公告)号：US08274420B2
公开(公告)日：2012-09-25
申请号：US12970861
申请日：2010-12-16
申请人： Hyun Kyu Yu , Seon Ho Han , Young Hwa Kim , Seong Hwan Cho
发明人： Hyun Kyu Yu , Seon Ho Han , Young Hwa Kim , Seong Hwan Cho
IPC分类号： H03M1/38
CPC分类号： H03M1/46 , H03M1/827
摘要： There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code.
摘要翻译：提供了仅包括最小电容器以执行模数转换操作的逐次逼近模数转换器，从而使得可以具有非常强的工艺变化电阻特性，同时具有减小的电容和电路面积。逐次逼近模数转换器可以包括提供参考电流的参考电流提供单元; 信号存储单元，存储通过对参考电流进行充电而产生的参考信号和从外部输入的输入信号; 比较单元，其比较所述参考信号和所述输入信号; 以及控制器，其基于所述比较单元的比较结果来控制所述参考电流供给单元，同时根据所述二进制码来改变提供给所述信号存储单元的参考电流的供给量。

3. 发明授权

US08306498B2 Wideband receiver 有权
标题翻译：宽带接收机
公开(公告)号：US08306498B2
公开(公告)日：2012-11-06
申请号：US12970874
申请日：2010-12-16
申请人： Hyun Kyu Yu , Joon Hee Lee , Seong Hwan Cho
发明人： Hyun Kyu Yu , Joon Hee Lee , Seong Hwan Cho
IPC分类号： H04B1/18 , H04K3/00
CPC分类号： H04B1/28 , H03D7/1441 , H03D7/1458
摘要： Provided is a wideband receiver that has a smaller area and consumes less power and can prevent harmonic mixing occurring due to an increase in the number of communications systems using wideband. A wideband receiver according to an aspect of the invention may include: an front-end unit receiving and performing low-pass filtering on a wideband input signal in a continuous-time domain; and a down-conversion unit sampling and holding an output signal of the front-end unit according to a local oscillator signal and performing low-pass filtering on the output signal in a discrete tie domain.
摘要翻译：提供了一种宽带接收机，其具有较小的面积并且消耗更少的功率，并且可以防止由于使用宽带的通信系统的数量的增加而发生谐波混合。根据本发明的一个方面的宽带接收机可以包括：前端单元在连续时域中接收并对宽带输入信号执行低通滤波; 下变频单元根据本地振荡器信号对前端单元的输出信号进行采样和保持，并对离散的连接域中的输出信号进行低通滤波。

4. 发明授权

US08509353B2 Digital receiver 有权
标题翻译：数字接收机
公开(公告)号：US08509353B2
公开(公告)日：2013-08-13
申请号：US12818510
申请日：2010-06-18
申请人： Seon-Ho Han , Hyun Kyu Yu
发明人： Seon-Ho Han , Hyun Kyu Yu
IPC分类号： H03K9/00
CPC分类号： H04B1/0025 , H04B1/001
摘要： In a digital receiver, a noise attenuation and signal magnitude mapping variable amplifying unit includes a filter and an amplifier, amplifies and band-bass filters an analog signal and attenuating white noise and an interference signal other than a band signal. An ADC performs subsampling on a carrier frequency of a desired signal and performs oversampling on the band of the desired signal by using a sampling frequency to convert the analog signal which has passed through the noise attenuation and signal magnitude mapping variable amplifying unit into a digital signal of a direct conversion frequency band or an intermediate frequency band. The ADC has a dynamic range for processing both the desired signal and an undesired signal adjacent to the desired signal. A digital signal processing unit converts a signal frequency of the digital signal or digital-filters an undesired signal within the digital signal and processes the digital signal by digitally adjusting a gain.
摘要翻译：在数字接收机中，噪声衰减和信号幅度映射可变放大单元包括滤波器和放大器，对模拟信号进行放大和频带滤波，并衰减白噪声和除频带信号之外的干扰信号。 ADC在期望信号的载波频率上执行子采样，并通过使用采样频率对已经通过噪声衰减和信号幅度映射可变放大单元的模拟信号进行数字信号的期望信号的频带上的过采样，的直接转换频带或中频带。 ADC具有用于处理期望信号和与期望信号相邻的不期望信号的动态范围。数字信号处理单元转换数字信号的信号频率或数字滤波数字信号内的不需要的信号，并通过数字调节增益来处理数字信号。

5. 发明申请

US20130064148A1 SINGLE FREQUENCY SYNTHESIZER BASED FDD TRANSCEIVER 有权
标题翻译：单频合成器FDD收发器
公开(公告)号：US20130064148A1
公开(公告)日：2013-03-14
申请号：US13608677
申请日：2012-09-10
申请人： Hyun Ho BOO , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
发明人： Hyun Ho BOO , Seon-Ho Han , Jang Hong Choi , Ik Soo Eo , Hyun Kyu Yu
IPC分类号： H04J1/02
CPC分类号： H04L27/3836 , H04B1/0007 , H04L27/206 , H04L27/2092 , H04L27/2332 , H04L27/362 , H04L27/3854
摘要： The present invention relates to a single frequency synthesizer based FDD transceiver. A single frequency synthesizer generates and provides a carrier frequency so that frequency up-conversion and frequency down-conversion can be performed at the time of transmission and reception. Accordingly, the area, power consumption, and design complexity of the entire system can be reduced, and the performance of the system can be improved.
摘要翻译：本发明涉及一种基于单频合成器的FDD收发器。单个频率合成器产生并提供载波频率，使得可以在发送和接收时执行上变频和下变频。因此，可以降低整个系统的面积，功耗和设计复杂性，并且可以提高系统的性能。

6. 发明申请

US20130063199A1 PROGRAMMABLE COMPLEX MIXER 审中-公开
标题翻译：可编程复合混合器
公开(公告)号：US20130063199A1
公开(公告)日：2013-03-14
申请号：US13615423
申请日：2012-09-13
申请人： Seon-Ho HAN , Hyun Ho Boo , Mun Yang Park , Jang Hong Choi , Hyun Kyu Yu
发明人： Seon-Ho HAN , Hyun Ho Boo , Mun Yang Park , Jang Hong Choi , Hyun Kyu Yu
IPC分类号： G06G7/14
CPC分类号： H03D7/165
摘要： Disclosed is a programmable complex mixer. In accordance with the embodiments of the present invention, it is possible to control an output by programming paths and signs of internal signals in a complex mixer to reduce a processing bandwidth, power consumption, and a chip area in a transceiver, thereby improving performance of a transceiver.
摘要翻译：公开了一种可编程复合混合器。根据本发明的实施例，可以通过在复合混频器中编程内部信号的路径和符号来控制输出，以减少收发器中的处理带宽，功耗和芯片面积，从而提高收发器

7. 发明授权

US08344772B2 Time-to-digital converter and all digital phase-locked loop including the same 有权
标题翻译：时间到数字转换器和所有数字锁相环包括相同的
公开(公告)号：US08344772B2
公开(公告)日：2013-01-01
申请号：US12956498
申请日：2010-11-30
申请人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
发明人： Ja Yol Lee , Seon Ho Han , Mi Jeong Park , Jang Hong Choi , Seong Do Kim , Hyun Kyu Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , G04F10/005 , H03L7/085 , H03L7/103 , H03L2207/50
摘要： An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.
摘要翻译：全数字锁相环（ADPLL）包括：相位计数器累积频率设定字值和数字控制振荡器（DCO）时钟的相位，并检测参考时钟和重新定时钟之间的精细相位差; 相位检测器，根据所述精细相位差检测补偿所述频率设定字值与所述DCO时钟之间的相位差的数字相位误差值，以检测数字相位误差值; 数字环路滤波器滤除数字相位误差值并控制PLL的操作特性; 锁定检测器，根据数字环路滤波器的输出产生锁定指示信号; 数字控制振荡器根据数字环路滤波器的输出改变DCO时钟的频率; 以及重新计时的时钟发生器，通过以低频再定时DCO时钟产生重定时钟。

8. 发明授权

US07884673B2 Wideband low-noise amplifier 有权
标题翻译：宽带低噪声放大器
公开(公告)号：US07884673B2
公开(公告)日：2011-02-08
申请号：US12423764
申请日：2009-04-14
申请人： Seon Ho Han , Cheon Soo Kim , Jae Young Kim , Hyun Kyu Yu
发明人： Seon Ho Han , Cheon Soo Kim , Jae Young Kim , Hyun Kyu Yu
IPC分类号： H03F3/04
CPC分类号： H03F1/26 , H03F1/565 , H03F3/195 , H03F2200/222 , H03F2200/294 , H03F2200/36 , H03F2200/451
摘要： A wideband low-noise amplifier includes a source-degenerated common-source amplifier, a common-gate amplifier, and a matching frequency band determiner. The source-degenerated common-source amplifier is configured to amplify an input signal to output a first signal that is opposite in phase to the input signal. The common-gate amplifier is connected in parallel to the source-degenerated common-source amplifier to amplify the input signal to output a second signal that has the same phase as the input signal. The matching frequency band determiner is configured to isolate an input terminal of the source-degenerated common-source amplifier and an input terminal of the common-gate amplifier and determine a matching frequency band.
摘要翻译：宽带低噪声放大器包括源极退化的共源放大器，共栅放大器和匹配的频带确定器。源极退化的共源放大器被配置为放大输入信号以输出与输入信号相位相反的第一信号。共栅放大器与源极简并公共源放大器并联连接，以放大输入信号以输出与输入信号具有相同相位的第二信号。匹配频带确定器被配置为隔离源极退化的共源极放大器的输入端和公共栅极放大器的输入端，并确定匹配的频带。

9. 发明申请

US20100135446A1 DIGITAL-INTENSIVE RF RECEIVER 审中-公开
标题翻译：数字强度射频接收机
公开(公告)号：US20100135446A1
公开(公告)日：2010-06-03
申请号：US12629684
申请日：2009-12-02
申请人： Seon Ho Han , Jae Hoon Shim , Hyun Kyu Yu
发明人： Seon Ho Han , Jae Hoon Shim , Hyun Kyu Yu
IPC分类号： H04B1/10
CPC分类号： H04B1/001 , H04B1/0025
摘要： A digital-intensive RF receiver including: a first filter unit configured to allow an RF signal of a pre-set frequency band among RF signals to pass therethrough; a low noise amplifier (LNA) configured to amplify the RF signal from the first filter unit such that the RF signal has a pre-set magnitude; a second filter unit configured to allow an RF signal of a pre-set frequency band among RF signals from the LNA to pass therethrough; a clock generation unit configured to generate a pre-set reference frequency signal and generate a sub-sampling clock having a pre-set frequency lower than an RF carrier frequency by using the reference frequency signal; a sub-sampling A/D conversion unit configured to A/D-convert the RF signal from the second filter unit into a digital signal according to the sub-sampling clock from the clock generation unit, divide the RF signal into a plurality of frequency bands and sub-sample them during the A/D conversion process and perform noise shaping by the sub-channels included in the RF signal; and a digital processing unit configured to process a digital signal from the sub-sampling A/D conversion unit according to a system clock generated by using the reference frequency signal from the clock generation unit.
摘要翻译：一种数字密集RF接收机，包括：第一滤波器单元，被配置为允许RF信号中的预设频带的RF信号通过; 低噪声放大器（LNA），被配置为放大来自第一滤波器单元的RF信号，使得RF信号具有预设的幅度; 第二滤波器单元，被配置为允许来自所述LNA的RF信号中的预设频带的RF信号通过; 时钟生成单元，被配置为通过使用所述参考频率信号来生成预设参考频率信号并生成具有低于RF载波频率的预置频率的子采样时钟; 子采样A / D转换单元，被配置为根据来自时钟生成单元的子采样时钟将来自第二滤波器单元的RF信号进行A / D转换为数字信号，将RF信号分成多个频率在A / D转换过程中对它们进行子采样，并通过RF信号中包含的子信道进行噪声整形; 以及数字处理单元，被配置为根据通过使用来自时钟生成单元的参考频率信号产生的系统时钟来处理来自子采样A / D转换单元的数字信号。

10. 发明授权

US06615398B2 Method for dividing ROM and DDFS using the same method 有权
公开(公告)号：US06615398B2
公开(公告)日：2003-09-02
申请号：US10017315
申请日：2001-12-18
申请人： Hyun Kyu Yu , Seon-Ho Han , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Lee-Sup Kim , Ki-Hyuk Sung , Byung-Do Yang , Young-Jun Kim
发明人： Hyun Kyu Yu , Seon-Ho Han , Mun Yang Park , Seong-Do Kim , Yong-Sik Youn , Lee-Sup Kim , Ki-Hyuk Sung , Byung-Do Yang , Young-Jun Kim
IPC分类号： G06F1750
CPC分类号： G06F1/0356 , G06F1/0328 , G06F2101/04 , G11C17/00
摘要： The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式