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1. 发明授权

US09250831B1 Isolated shared memory architecture (iSMA) 有权
标题翻译：隔离共享内存架构（iSMA）
公开(公告)号：US09250831B1
公开(公告)日：2016-02-02
申请号：US14194574
申请日：2014-02-28
申请人： INPHI CORPORATION
发明人： Nirmal Raj Saxena , Sreenivas Krishnan , David Wang
IPC分类号： G06F12/10 , G06F3/06 , G06F13/40 , G06F12/08
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0613 , G06F3/0635 , G06F3/0644 , G06F3/0658 , G06F3/067 , G06F3/0679 , G06F3/0688 , G06F12/0813 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Techniques for a massively parallel and memory centric computing system. The system has a plurality of processing units operably coupled to each other through one or more communication channels. Each of the plurality of processing units has an ISMn interface device. Each of the plurality of ISMn interface devices is coupled to an ISMe endpoint connected to each of the processing units. The system has a plurality of DRAM or Flash memories configured in a disaggregated architecture and one or more switch nodes operably coupling the plurality of DRAM or Flash memories in the disaggregated architecture. The system has a plurality of high speed optical cables configured to communicate at a transmission rate of 100 G or greater to facilitate communication from any one of the plurality of processing units to any one of the plurality of DRAM or Flash memories.
摘要翻译：大规模并行和以内存为中心的计算系统的技术。该系统具有通过一个或多个通信信道彼此可操作地耦合的多个处理单元。多个处理单元中的每一个具有ISMn接口装置。多个ISMn接口设备中的每一个耦合到连接到每个处理单元的ISMe端点。该系统具有以分解体系结构配置的多个DRAM或闪存，以及可操作地以分解结构耦合多个DRAM或闪速存储器的一个或多个交换节点。该系统具有多个高速光缆，其配置为以100G或更大的传输速率进行通信，以便于从多个处理单元中的任何一个到多个DRAM或闪存中的任何一个的通信。

2. 发明授权

US08996960B1 Vertical error correction code for DRAM memory 有权
标题翻译： DRAM存储器的垂直纠错码
公开(公告)号：US08996960B1
公开(公告)日：2015-03-31
申请号：US13797583
申请日：2013-03-12
申请人： Inphi Corporation
发明人： Nirmal Raj Saxena , David Wang , Hamid Rategh , Lawrence Tse
IPC分类号： G11C29/00 , H03M13/17
CPC分类号： H03M13/17 , G06F11/1048
摘要： Techniques for operating a DIMM apparatus. The apparatus comprises a plurality of DRAM devices numbered from 0 through N−1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N−1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of DRAM devices.
摘要翻译：操作DIMM装置的技术。该装置包括从0到N-1编号的多个DRAM器件，其中N是大于7（7）的整数，每个DRAM器件被配置在衬底模块中; 包括从0到N-1编号的多个数据缓冲器（DB）的缓冲器集成电路器件，其中N是大于7（7）的整数，每个数据缓冲器对应于一个DRAM器件; 以及与多个DRAM设备相关联的多个纠错模块（“ECM”）。

3. 发明授权

US09142279B2 DRAM refresh method and system 有权
标题翻译： DRAM刷新方法和系统
公开(公告)号：US09142279B2
公开(公告)日：2015-09-22
申请号：US14242292
申请日：2014-04-01
申请人： INPHI CORPORATION
发明人： David Wang
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40607 , G11C11/40618
摘要： A DRAM refresh method used with a memory system organized into rows of memory cells, each of which has an associated data retention time, with the system arranged to refresh predefined blocks of memory cells simultaneously. For each block of memory cells that are to be refreshed simultaneously, the minimum data retention time for the memory cells in the block is determined. Then, an asymmetric refresh sequence is created which specifies the order in which the blocks of memory cells are refreshed, such that the blocks having the shortest minimum data retention times are refreshed more often than the blocks having longer minimum data retention times.
摘要翻译： DRAM刷新方法与存储器系统一起使用，存储器系统被组织成行的存储器单元，每个存储器单元具有相关的数据保留时间，系统被布置为同时刷新存储器单元的预定义块。对于要同时刷新的每个存储单元块，确定块中存储单元的最小数据保留时间。然后，创建不对称刷新序列，其指定刷新存储器单元的块的顺序，使得具有最短最小数据保留时间的块比具有较长最小数据保留时间的块更频繁地刷新。

4. 发明授权

US08854908B1 System and method for memory access in server communications 有权
标题翻译：服务器通信中内存访问的系统和方法
公开(公告)号：US08854908B1
公开(公告)日：2014-10-07
申请号：US13797814
申请日：2013-03-12
申请人： Inphi Corporation
发明人： Andrew Burstein , David Wang
IPC分类号： G11C29/00 , G11C29/52
CPC分类号： G11C29/52 , G11C5/04 , G11C29/44 , G11C29/846
摘要： A random access memory includes a plurality of memories configured to store and provide data, and a test module coupled to the plurality of memories, wherein the test module is configured to write a first write data pattern into at last a first portion of the plurality of memories in response to a data pattern value, wherein the test module is configured to read a read data pattern from the plurality of memories, wherein the test module is configured to compare the first write data pattern to the read data pattern, and wherein the test module is configured to report errors in response to a comparison of the write data pattern to the read data pattern.
摘要翻译：随机存取存储器包括被配置为存储和提供数据的多个存储器以及耦合到所述多个存储器的测试模块，其中所述测试模块被配置为将第一写入数据模式写入到所述多个存储器的第一部分响应于数据模式值的存储器，其中所述测试模块被配置为从所述多个存储器读取读取数据模式，其中所述测试模块被配置为将所述第一写入数据模式与所读取的数据模式进行比较，并且其中所述测试模块被配置为响应于写数据模式与读数据模式的比较来报告错误。

5. 发明授权

US09015558B2 Systems and methods for error detection and correction in a memory module which includes a memory buffer 有权
标题翻译：包括存储器缓冲器的存储器模块中用于错误检测和校正的系统和方法
公开(公告)号：US09015558B2
公开(公告)日：2015-04-21
申请号：US14228847
申请日：2014-03-28
申请人： Inphi Corporation
发明人： David Wang , Christopher Haywood
IPC分类号： G11C29/00 , G06F11/10 , G11C7/10 , G11C11/408 , G11C29/52 , H03M13/15 , G11C29/04
CPC分类号： G06F11/1068 , G06F11/10 , G11C7/1006 , G11C11/408 , G11C29/52 , G11C29/848 , G11C2029/0411 , H03M13/1515 , H03M13/152
摘要： The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.
摘要翻译：本系统包括存储模块，该存储器模块包含多个RAM芯片，通常为DRAM，以及一个存储器缓冲器，用于缓冲DRAM和主机控制器之间的数据。存储器缓冲器包括错误检测和校正电路，其布置成确保存储的数据字的完整性。可以实现这一点的一种方式是通过计算每个数据字的奇偶校验位并将它们与每个数据字并行存储。如果主机控制器包括自己的错误检测和校正电路，则可以将错误检测和校正电路设置为检测和纠正单个错误或多个错误。或者，可以确定故障存储单元的位置并将其存储在地址匹配表中，该地址匹配表然后被用于控制将故障单元周围的数据引导到冗余DRAM芯片或在另一实施例中的嵌入式SRAM。

6. 发明授权

US09348539B1 Memory centric computing 有权
标题翻译：以内存为中心的计算
公开(公告)号：US09348539B1
公开(公告)日：2016-05-24
申请号：US14194416
申请日：2014-02-28
申请人： INPHI CORPORATION
发明人： Nirmal Raj Saxena , David Wang , Christopher Haywood , Eric McDonald , Chao Xu
IPC分类号： G06F3/06
CPC分类号： G11C11/005 , G11C5/04
摘要： A hybrid memory system. This system can include a processor coupled to a hybrid memory buffer (HMB) that is coupled to a plurality of DRAM and a plurality of Flash memory modules. The HMB module can include a Memory Storage Controller (MSC) module and a Near-Memory-Processing (NMP) module coupled by a SerDes (Serializer/Deserializer) interface. This system can utilize a hybrid (mixed-memory type) memory system architecture suitable for supporting low-latency DRAM devices and low-cost NAND flash devices within the same memory sub-system for an industry-standard computer system.
摘要翻译：混合存储器系统。该系统可以包括耦合到耦合到多个DRAM和多个闪存模块的混合存储器缓冲器（HMB）的处理器。 HMB模块可以包括由SerDes（串行器/解串器）接口耦合的存储器存储控制器（MSC）模块和近端存储器处理（NMP）模块。该系统可以利用混合（混合存储器型）存储器系统架构，其适用于在用于工业标准计算机系统的相同存储器子系统中支持低延迟DRAM设备和低成本NAND闪存器件。

7. 发明授权

US09123441B1 Backward compatible dynamic random access memory device and method of testing therefor 有权
标题翻译：向后兼容的动态随机存取存储器件及其测试方法
公开(公告)号：US09123441B1
公开(公告)日：2015-09-01
申请号：US14245991
申请日：2014-04-04
申请人： INPHI CORPORATION
发明人： David Wang
IPC分类号： G11C5/02 , G11C29/00
CPC分类号： G11C29/50016 , G11C11/401 , G11C29/44
摘要： A method for testing a memory device. The method can include coupling the memory device to a test apparatus and determining whether each of the memory cells in the memory device is within a first specification range. Each of the cells that fall outside of the first range can be identified. Each of the cells that meet the second specification range can be tested. The method can include selecting a tile associated with a highest number of cells that fall outside of the second range. A resource can then be used to repair each of the cells that fall outside of the second range for a tile associated with a fewer number of cells that fall outside of the second range such that a first number of tiles meets the first range and a second number of tiles meets the second range such that the first number the second number.
摘要翻译：一种用于测试存储器件的方法。该方法可以包括将存储器件耦合到测试装置并确定存储器件中的每个存储器单元是否在第一规格范围内。可以识别落在第一范围之外的每个细胞。可以测试满足第二规格范围的每个电池。该方法可以包括选择与第二范围之外的最大数量的单元相关联的瓦片。然后，可以使用资源来修复落在第二范围之外的每个小区，用于与较少数量的落在第二范围之外的小区相关联的瓦片，使得第一数量的瓦片满足第一范围，并且第二个瓦数满足第二范围，使第一个数字为第二个数字。

8. 发明授权

US08966327B1 Protocol checking logic circuit for memory system reliability 有权
标题翻译：协议检查逻辑电路，用于存储系统的可靠性
公开(公告)号：US08966327B1
公开(公告)日：2015-02-24
申请号：US13797623
申请日：2013-03-12
申请人： Inphi Corporation
发明人： David Wang
IPC分类号： G06F11/07 , G06F12/00 , G06F11/14
CPC分类号： G06F11/1076 , G06F11/008 , G06F11/1004 , G06F11/1016 , G06F12/00
摘要： A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.
摘要翻译：缓冲器集成电路器件。所述装置包括形成在所述衬底构件上的输出驱动器，所述输出驱动器至少具有命令总线和地址总线。该设备具有协议和奇偶校验块（“块”）。该设备具有在该块中配置的表。该表可以用多个定时参数来编程。该设备具有耦合到该表的存储器状态块和耦合到该表的命令历史表，以处理通过该块的所有命令的协议信息。缓冲器集成电路器件利用协议检查功能来防止故障传播，并且即使在主机存储器控制器故障或者来自主机存储器控制器的命令，控制和地址总线上的任何信号或信号的系统级故障的情况下也能够进行数据保护到缓冲器集成器件。

9. 发明授权

US09349433B2 Hidden refresh of weak memory storage cells in semiconductor memory 有权
标题翻译：半导体存储器中的弱存储器存储单元的隐藏刷新
公开(公告)号：US09349433B2
公开(公告)日：2016-05-24
申请号：US14175857
申请日：2014-02-07
申请人： INPHI CORPORATION
发明人： David Wang
IPC分类号： G11C8/00 , G11C11/4063 , G11C11/406 , G11C11/4076
CPC分类号： G11C11/4063 , G11C11/40611 , G11C11/4076
摘要： In an example, the present invention provides a computing system. The system has a memory interface device comprising a counter, a dynamic random access memory device coupled to the memory interface device. The device comprises a plurality of banks, each of the banks having a subarray, each subarray having a plurality of memory cells. The device has a data interface coupled to the plurality of banks. The device has an address interface coupled to the plurality of banks, and a particular pre-charge command configured to be transferred to the memory interface device. The counter is adapted to count a measured time duration from a first time when data are available at the data interface to a second time when a pre-charge command is received by the address interface.
摘要翻译：在一个示例中，本发明提供一种计算系统。该系统具有包括计数器，耦合到存储器接口设备的动态随机存取存储器设备的存储器接口设备。该设备包括多个存储体，每个存储体具有子阵列，每个子阵列具有多个存储单元。该设备具有耦合到多个存储体的数据接口。该设备具有耦合到多个存储区的地址接口，以及被配置为传送到存储器接口设备的特定预充电命令。该计数器适于对数据接口上的数据可用的第一次计数到第二次当地址接口接收到预充电命令时的测量持续时间。

10. 发明授权

US09317366B2 Protocol checking logic circuit for memory system reliability 有权
公开(公告)号：US09317366B2
公开(公告)日：2016-04-19
申请号：US14593257
申请日：2015-01-09
申请人： INPHI CORPORATION
发明人： David Wang
IPC分类号： G06F11/07 , G06F11/10 , G06F12/00 , G06F11/00
CPC分类号： G06F11/1076 , G06F11/008 , G06F11/1004 , G06F11/1016 , G06F12/00
摘要： A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

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