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1. 发明授权

US09952651B2 Deterministic current based frequency optimization of processor chip 有权
公开(公告)号：US09952651B2
公开(公告)日：2018-04-24
申请号：US14814870
申请日：2015-07-31
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Michael S. Floyd , Joshua D. Friedrich , Charles R. Lefurgy , Kirk D. Peterson , Karthick Rajamani , Srinivasan Ramani , Todd J. Rosedahl , Gregory S. Still , Brian W. Thompto , Victor Zyuban
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3206 , G06F1/3243 , Y02D10/126 , Y02D10/152
摘要： A system for adjusting a frequency of a processor is disclosed herein. The system includes a processor and a memory, where the memory includes a program configured to adjust a frequency of a multi-core processor. The operations include determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The operations also include calculating a switching current by subtracting the leakage current from the total current and calculating an effective switching capacitance based at least in part on the switching current. The operations also include calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

2. 发明申请

US20150293844A1 BROADCAST AND UNICAST COMMUNICATION BETWEEN NON-COHERENT PROCESSORS USING COHERENT ADDRESS OPERATIONS 有权
标题翻译：使用相关地址操作的非相关处理器之间的广播和短信通信
公开(公告)号：US20150293844A1
公开(公告)日：2015-10-15
申请号：US14248653
申请日：2014-04-09
申请人： International Business Machines Corporation
发明人： Gregory S. Still
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F13/1673 , G06F12/0837 , G06F12/1072 , G06F13/4221 , G06F2212/657
摘要： Non-address data is received for transmission on a non-transitory communication medium communicably coupling a plurality of devices, wherein the communication medium includes an address component and a data transport component separate from the address component. At least a portion of the non-address data is inserted into a portion of an address command. An indicator is set in the address command to notify a receiver that the information received in the address command over the address component is not associated with a memory address. The address command containing the non-address data is then sent over the address component of the communication medium.
摘要翻译：接收非地址数据以在可通信地耦合多个设备的非暂时通信介质上进行传输，其中通信介质包括与地址组件分离的地址组件和数据传输组件。非地址数据的至少一部分被插入到地址命令的一部分中。在地址命令中设置指示符，以通知接收者地址组件中的地址命令中接收的信息不与存储器地址相关联。然后通过通信介质的地址组件发送包含非地址数据的地址命令。

3. 发明申请

US20150061744A1 PASSGATE STRENGTH CALIBRATION TECHNIQUES FOR VOLTAGE REGULATORS 有权
标题翻译：用于电压调节器的优化精度校准技术
公开(公告)号：US20150061744A1
公开(公告)日：2015-03-05
申请号：US14458428
申请日：2014-08-13
申请人： International Business Machines Corporation
发明人： John F. Bulzacchelli , Zeynep Toprak Deniz , Joshua D. Friedrich , Tilman Gloekler , Gregory S. Still
IPC分类号： G05F1/625
CPC分类号： G05F1/59 , G05F1/625
摘要： Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.
摘要翻译：提供系统和方法来调节负载电路的电源电压。例如，系统包括包括通路装置的电压调节器电路。该系统包括通道强度校准控制模块，其被配置为（i）获得指定电压调节器电路的操作条件的信息，（ii）使用获得的信息访问一个或多个查找表的访问条目，（iii）使用在所访问的条目内的信息以确定由所获得的信息指定的操作条件下负载电路可能要求的最大负载电流，并且预测足以提供所确定的最大负载电流的通道装置宽度，以及（iv ）根据预测的通道装置宽度设置通道装置的有效宽度。

4. 发明申请

US20140167832A1 CHANGING RESONANT CLOCK MODES 有权
标题翻译：改变时钟模式
公开(公告)号：US20140167832A1
公开(公告)日：2014-06-19
申请号：US13719408
申请日：2012-12-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas J. Bucelot , Alan Drake , Joshua D. Friedrich , Jason D. Hibbeler , Liang-Teck Pang , William R. Reohr , Phillip John Restle , Gregory S. Still , Michael G.R. Thomson
IPC分类号： H03K3/00
CPC分类号： G06F1/10
摘要： Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.
摘要翻译：描述了具有能够从非共振时钟模式转换到第一谐振时钟模式的时钟分配网络的集成电路。在一系列时钟周期内，逐渐完成在时钟模式之间或各种谐振时钟频率之间的转换。例如，当从非共振时钟模式转换到第一谐振时钟模式时，时钟扇区驱动器的强度在一系列时钟周期内减小，并且与谐振电路相关联的多个谐振开关中的各个谐振开关被修改协调减少时钟扇区驱动程序的实力。

5. 发明申请

US20140149763A1 COMPUTING SYSTEM VOLTAGE CONTROL 有权
标题翻译：计算系统电压控制
公开(公告)号：US20140149763A1
公开(公告)日：2014-05-29
申请号：US13773841
申请日：2013-02-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Malcolm S. Allen-Ware , Bishop Brock , Tilman Gloekler , Timothy G. Hallett , Charles R. Lefurgy , Karthick Rajamani , Guillermo J. Silva , Gregory S. Still
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3296 , Y02D10/172
摘要： Computing system voltage control methods include receiving an indication of a first performance state. The first performance state is associated with a first voltage and applies to at least one computing system component. The indication of the first performance state is received by a first computing system component from a second computing system component. An indication of a second performance state is received, wherein the second performance state is associated with a second voltage that is not equal to the first voltage. It is determined whether the second performance state is within a range defined by a minimum performance state and a maximum performance state. Responsive to determining that the second performance state is within the range defined by the minimum performance state and the maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state.
摘要翻译：计算系统电压控制方法包括接收第一性能状态的指示。第一性能状态与第一电压相关联并且应用于至少一个计算系统组件。由第一计算系统组件从第二计算系统组件接收第一性能状态的指示。接收第二性能状态的指示，其中第二性能状态与不等于第一电压的第二电压相关联。确定第二性能状态是否在由最低性能状态和最大性能状态限定的范围内。响应于确定第二性能状态在由最小性能状态和最大性能状态限定的范围内的情况下，将至少一个计算系统组件的电压设置为等于与第二执行状态相关联的电压。

6. 发明授权

US09778726B2 Deterministic current based frequency optimization of processor chip 有权
公开(公告)号：US09778726B2
公开(公告)日：2017-10-03
申请号：US14833324
申请日：2015-08-24
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Michael S. Floyd , Joshua D. Friedrich , Charles R. Lefurgy , Kirk D. Peterson , Karthick Rajamani , Srinivasan Ramani , Todd J. Rosedahl , Gregory S. Still , Brian W. Thompto , Victor Zyuban
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3206 , G06F1/3243 , Y02D10/126 , Y02D10/152
摘要： A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes determining a total current and a temperature of the multi-core processor and estimating a leakage current for the multi-core processor. The method also includes calculating a switching current by subtracting the leakage current from the total current. The method also includes calculating an effective switching capacitance based at least in part on the switching current. The method also includes calculating a workload activity factor by dividing the effective switching capacitance by a predetermined effective switching capacitance stored in vital product data, and enforcing a turbo frequency limit of the multi-core processor based on the workload activity factor.

7. 发明授权

US09514068B2 Broadcast and unicast communication between non-coherent processors using coherent address operations 有权
标题翻译：使用相干地址操作的非相干处理器之间的广播和单播通信
公开(公告)号：US09514068B2
公开(公告)日：2016-12-06
申请号：US14300882
申请日：2014-06-10
申请人： International Business Machines Corporation
发明人： Gregory S. Still
IPC分类号： G06F13/12 , G06F13/16 , G06F12/10 , G06F13/42 , G06F12/08 , G06F3/00
CPC分类号： G06F13/1673 , G06F12/0837 , G06F12/1072 , G06F13/4221 , G06F2212/657
摘要： Non-address data is received that is to be transmitted on a non-transitory communication medium communicably coupling a plurality of devices, wherein the communication medium includes an address component and a data transport component separate from the address component. At least a portion of the non-address data is inserted into a portion of an address command. An indicator is set in the address command to notify a receiver that the information received in the address command over the address component is not associated with a memory address. The address command containing the non-address data is then sent over the address component of the communication medium.
摘要翻译：接收要在可通信地耦合多个设备的非暂时通信介质上发送的非地址数据，其中通信介质包括与地址组件分离的地址组件和数据传输组件。非地址数据的至少一部分被插入到地址命令的一部分中。在地址命令中设置指示符，以通知接收者地址组件中的地址命令中接收的信息不与存储器地址相关联。然后通过通信介质的地址组件发送包含非地址数据的地址命令。

8. 发明授权

US09182797B2 Decoupled power and performance allocation in a multiprocessing system 有权
标题翻译：多处理系统中的分离功率和性能分配
公开(公告)号：US09182797B2
公开(公告)日：2015-11-10
申请号：US13762538
申请日：2013-02-08
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Bishop Brock , Tilman Gloekler , Timothy G. Hallett , Karthick Rajamani , Todd J. Rosedahl , Guillermo J. Silva , Gregory S. Still
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Embodiments of the inventive subject matter include setting minimum and maximum performance operating limits for each of a plurality of controllers. The operating limits are set in accordance with performance rules imposed on the system. In response to a request to change operation of a processing unit to a requested operational setting, it is determined whether the requested operational setting complies with the minimum and maximum performance operating limits. The minimum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the minimum performance operating limit. The maximum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the maximum performance operating limit. The requested operational setting is sent to a performance controller if the requested operational setting complies with the minimum and maximum performance operating limits.
摘要翻译：本发明的实施例包括为多个控制器中的每一个设置最小和最大性能操作限制。操作限制根据系统上施加的性能规则设置。响应于将处理单元的操作改变为所请求的操作设置的请求，确定所请求的操作设置是否符合最小和最大性能操作限制。如果所请求的操作设置不符合最低性能运行限制，则最低性能运行限制将发送到性能控制器。如果所请求的操作设置不符合最高性能运行限制，则性能最大运行限制将发送到性能控制器。如果请求的操作设置符合最低和最高性能运行限制，则所请求的操作设置将发送到性能控制器。

9. 发明申请

US20150123633A1 PASSGATE STRENGTH CALIBRATION TECHNIQUES FOR VOLTAGE REGULATORS 有权
公开(公告)号：US20150123633A1
公开(公告)日：2015-05-07
申请号：US14595850
申请日：2015-01-13
申请人： International Business Machines Corporation
发明人： John F. Bulzacchelli , Zeynep Toprak Deniz , Joshua D. Friedrich , Tilman Gloekler , Gregory S. Still
IPC分类号： G05F1/59
CPC分类号： G05F1/59 , G05F1/625
摘要： Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.

10. 发明申请

US20140149762A1 DECOUPLED POWER AND PERFORMANCE ALLOCATION IN A MULTIPROCESSING SYSTEM 有权
标题翻译：在多处理系统中解码功率和性能分配
公开(公告)号：US20140149762A1
公开(公告)日：2014-05-29
申请号：US13762538
申请日：2013-02-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Malcolm S. Allen-Ware , Bishop Brock , Tilman Gloekler , Timothy G. Hallett , Karthick Rajamani , Todd J. Rosedahl , Guillermo J. Silva , Gregory S. Still
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Embodiments of the inventive subject matter include setting minimum and maximum performance operating limits for each of a plurality of controllers. The operating limits are set in accordance with performance rules imposed on the system. In response to a request to change operation of a processing unit to a requested operational setting, it is determined whether the requested operational setting complies with the minimum and maximum performance operating limits. The minimum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the minimum performance operating limit. The maximum performance operating limit is sent to a performance controller if the requested operational setting does not comply with the maximum performance operating limit. The requested operational setting is sent to a performance controller if the requested operational setting complies with the minimum and maximum performance operating limits.
摘要翻译：本发明的实施例包括为多个控制器中的每一个设置最小和最大性能操作限制。操作限制根据系统上施加的性能规则设置。响应于将处理单元的操作改变为所请求的操作设置的请求，确定所请求的操作设置是否符合最小和最大性能操作限制。如果所请求的操作设置不符合最低性能运行限制，则最低性能运行限制将发送到性能控制器。如果所请求的操作设置不符合最高性能运行限制，则性能最大运行限制将发送到性能控制器。如果请求的操作设置符合最低和最高性能运行限制，则所请求的操作设置将发送到性能控制器。

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