专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09250645B2 Circuit design for balanced logic stress 有权
标题翻译：平衡逻辑应力的电路设计
公开(公告)号：US09250645B2
公开(公告)日：2016-02-02
申请号：US14198790
申请日：2014-03-06
申请人： International Business Machines Corporation
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
IPC分类号： G06F1/08 , G06F13/20
CPC分类号： G06F1/08 , G06F13/20
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.
摘要翻译：公开了一种电子系统，其可以包括相位流水线，数据流水线，输入相位选择器和输出相位选择器。相位流水线可以具有由时钟信号计时的锁存器，并被设计成将相位信号从相位输入传播到相位输出。数据流水线可以具有由相位流水线时钟信号定时的锁存器，并被设计为将数据从数据输入传播到数据输出。输入相位选择器可以被设计为响应于相位输入处的数据，向数据输入端提供来自数据输入端的数据的反相或非反相副本到数据流水线数据输入端。输出相位选择器可以被设计为响应于相位流水线输出值，将来自数据流水线输出的数据的反相或非反相副本提供给输出相位选择器数据输出。

2. 发明申请

US20150115431A1 THERMAL ENERGY DISSIPATION USING BACKSIDE THERMOELECTRIC DEVICES 有权
标题翻译：使用背面热电装置进行热能消耗
公开(公告)号：US20150115431A1
公开(公告)日：2015-04-30
申请号：US14067507
申请日：2013-10-30
申请人： International Business Machines Corporation
发明人： Nathaniel R. Chadwick , Jeffrey P. Gambino , Kirk D. Peterson
IPC分类号： H01L23/38 , H01L35/30 , H01L35/34
CPC分类号： H01L23/38 , H01L35/30 , H01L35/34 , H01L2224/11 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a semiconductor structure and method to dissipate heat generated by semiconductor devices by utilizing backside thermoelectric devices. In certain embodiments, the semiconductor structure comprises an electronic device formed on a first side of the semiconductor structure. The semiconductor structure also comprises a thermoelectric cooling device formed on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction. In other embodiments, the method comprises forming an electronic device on a first side of a semiconductor structure. The method also comprises forming a thermoelectric cooling device on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction.
摘要翻译：本发明的实施例提供了通过利用背面热电装置来散发由半导体器件产生的热量的半导体结构和方法。在某些实施例中，半导体结构包括形成在半导体结构的第一侧上的电子器件。半导体结构还包括形成在半导体结构的第二侧上的热电冷却装置，其紧邻需要散热的半导体结构的区域，其中热电冷却装置包括珀尔帖结。在其他实施例中，该方法包括在半导体结构的第一侧上形成电子器件。该方法还包括在半导体结构的第二侧上形成热电冷却装置，该热电冷却装置紧邻希望散热的半导体结构的区域，其中热电冷却装置包括珀尔帖结。

3. 发明申请

US20180292878A1 ADAPTIVE FREQUENCY OPTIMIZATION IN PROCESSORS 审中-公开
公开(公告)号：US20180292878A1
公开(公告)日：2018-10-11
申请号：US15480963
申请日：2017-04-06
申请人： International Business Machines Corporation
发明人： Nathaniel R. Chadwick , Bjorn P. Christensen , James M. Crafts , Allen R Hall , Kevin F. Reick , Jon Robert Tetzloff
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/24 , G06F1/3243 , G06F1/3296
摘要： A processor can have a plurality of cores. A first core processor of a first core can read one or more values of a default parameter set. The first core can be operated in accordance with a first operating characteristic based, at least in part, on the one or more values of the default parameter set. The first core processor can receive an indication to change the operating characteristic of the first core processor. In response to receiving the indication to change the operating characteristic, a signal can be issued to the first core processor to reset. In response to the reset, the first core processor can read one or more values of an alternative parameter set. The first core processor can then be operated in accordance with a second operating characteristic based, at least in part, on the one or more values of the alternative parameter set.

4. 发明授权

US09520876B1 Power gating and clock gating in wiring levels 有权
标题翻译：电源门控和时钟门控接线电平
公开(公告)号：US09520876B1
公开(公告)日：2016-12-13
申请号：US15045753
申请日：2016-02-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nathaniel R. Chadwick , Tassbieh Hassan , Kirk D. Peterson , John E. Sheets, II , Christine E. Whiteside
IPC分类号： H03K19/00 , H03K19/177 , H03K3/037 , H03K19/096 , H03K19/0185 , H01L25/065 , H01L21/48 , H01L23/14 , H01L21/66 , H01L23/522 , G06F17/50
CPC分类号： H03K19/0016 , G06F13/385 , G06F13/4081 , G06F17/505 , G06F17/5063 , G06F17/5072 , G06F17/5077 , G06F2217/62 , G06F2217/78 , H01L21/486 , H01L22/32 , H01L23/147 , H01L23/522 , H01L25/0652 , H01L25/0657 , H03K19/018585 , H03K19/096 , H03K19/17728
摘要： A semiconductor comprising a front end of line portion including a logical processing unit (LPU) and a second LPU. The first LPU configured to perform a first operation and the second LPU configured to perform a second operation following the first operation. A back end of line portion including a plurality of wiring levels, and further including a power gate and a clock gate that are integrated into one or more wiring levels of the plurality of wiring levels. The power gate and clock gate are further electrically connected to the first LPU by an enable wire. The power gate and clock gate are electrically connected to a power grid and a clock net, respectively, by the enable wire, and the enable wire is further electrically connected to a latch of the second LPU. A signal wire is electrically connected to the first LPU and to the latch.
摘要翻译：一种半导体，包括包括逻辑处理单元（LPU）和第二LPU的线路部分的前端。所述第一LPU被配置为执行第一操作，并且所述第二LPU被配置为在所述第一操作之后执行第二操作。包括多个布线层的线路部分的后端，并且还包括集成在所述多个布线层的一个或多个布线层中的电源门和时钟门。功率门和时钟门通过使能线进一步电连接到第一LPU。功率门和时钟门分别通过使能线电连接到电网和时钟网，并且使能线进一步电连接到第二LPU的锁存器。信号线电连接到第一LPU和锁存器。

5. 发明申请

US20150253807A1 CIRCUIT DESIGN FOR BALANCED LOGIC STRESS 有权
公开(公告)号：US20150253807A1
公开(公告)日：2015-09-10
申请号：US14198790
申请日：2014-03-06
申请人： International Business Machines Corporation
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
IPC分类号： G06F1/08 , G06F13/20
CPC分类号： G06F1/08 , G06F13/20
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.

6. 发明授权

US09099427B2 Thermal energy dissipation using backside thermoelectric devices 有权
标题翻译：使用背面热电装置的热能耗散
公开(公告)号：US09099427B2
公开(公告)日：2015-08-04
申请号：US14067507
申请日：2013-10-30
申请人： International Business Machines Corporation
发明人： Nathaniel R. Chadwick , Jeffrey P. Gambino , Kirk D. Peterson
IPC分类号： H01L23/38 , H01L35/34 , H01L35/30
CPC分类号： H01L23/38 , H01L35/30 , H01L35/34 , H01L2224/11 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a semiconductor structure and method to dissipate heat generated by semiconductor devices by utilizing backside thermoelectric devices. In certain embodiments, the semiconductor structure comprises an electronic device formed on a first side of the semiconductor structure. The semiconductor structure also comprises a thermoelectric cooling device formed on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction. In other embodiments, the method comprises forming an electronic device on a first side of a semiconductor structure. The method also comprises forming a thermoelectric cooling device on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction.
摘要翻译：本发明的实施例提供了通过利用背面热电装置来散发由半导体器件产生的热量的半导体结构和方法。在某些实施例中，半导体结构包括形成在半导体结构的第一侧上的电子器件。半导体结构还包括形成在半导体结构的第二侧上的热电冷却装置，其紧邻需要散热的半导体结构的区域，其中热电冷却装置包括珀尔帖结。在其他实施例中，该方法包括在半导体结构的第一侧上形成电子器件。该方法还包括在半导体结构的第二侧上形成热电冷却装置，该热电冷却装置紧邻希望散热的半导体结构的区域，其中热电冷却装置包括珀尔帖结。

7. 发明授权

US08943458B1 Determining chip burn-in workload using emulated application condition 有权
标题翻译：使用模拟应用条件确定芯片老化工作量
公开(公告)号：US08943458B1
公开(公告)日：2015-01-27
申请号：US14027594
申请日：2013-09-16
申请人： International Business Machines Corporation
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
IPC分类号： G06F17/50
CPC分类号： G06F11/2236 , G06F11/263 , G11C29/06
摘要： Various embodiments include approaches for determining burn-in workload conditions for an integrated circuit (IC) design. Some embodiments include burn-in testing the IC design using the workload conditions. In some embodiments, a computer implemented method includes obtaining survey data about at least one application workload for an integrated circuit (IC) corresponding to an IC design; generating latch state and clocking statistics about the IC design for the at least one application workload based upon the survey data; and determining a set of burn-in workload conditions for the IC design based upon the latch state and clocking statistics about the IC design.
摘要翻译：各种实施例包括用于确定集成电路（IC）设计的老化工作负载条件的方法。一些实施例包括使用工作负载条件对IC设计进行老化测试。在一些实施例中，计算机实现的方法包括获得关于与IC设计相对应的集成电路（IC）的至少一个应用工作负载的调查数据; 基于所述调查数据产生关于所述至少一个应用工作负载的IC设计的锁存状态和时钟统计; 以及基于关于IC设计的锁存状态和时钟统计来确定用于IC设计的一组老化工作负载条件。

8. 发明授权

US09472269B2 Stress balancing of circuits 有权
标题翻译：电路的应力平衡
公开(公告)号：US09472269B2
公开(公告)日：2016-10-18
申请号：US14178955
申请日：2014-02-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Igor Arsovski , Nathaniel R. Chadwick , John B. Deforge , Ezra D. B. Hall , Kirk D. Peterson
IPC分类号： G11C11/419 , G11C29/06
CPC分类号： G11C11/419 , G11C29/06
摘要： Methods, systems, and structures for stress balancing field effect transistors subject to bias temperature instability-caused threshold voltage shifts. A method includes characterizing fatigue of a location in a memory array by skewing a bit line voltage of the location. The method also includes determining that the location is unbalanced based on the characterizing. Further, the method includes inverting a logic state of the location. Additionally, the method includes changing a value of an inversion indicator corresponding to the location.
摘要翻译：应力平衡场效应晶体管的方法，系统和结构受到偏置温度不稳定性引起的阈值电压偏移。一种方法包括通过偏移位置的位线电压来表征存储器阵列中的位置的疲劳。该方法还包括基于特征确定位置不平衡。此外，该方法包括反转位置的逻辑状态。此外，该方法包括改变对应于该位置的反转指示符的值。

9. 发明授权

US09437670B2 Light activated test connections 有权
标题翻译：光激活测试连接
公开(公告)号：US09437670B2
公开(公告)日：2016-09-06
申请号：US13689090
申请日：2012-11-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nathaniel R. Chadwick , John B. DeForge , John J. Ellis-Monaghan , Jeffrey P. Gambino , Ezra D. Hall , Marc D. Knox , Kirk D. Peterson
IPC分类号： G01R31/02 , H01L29/00 , H01L21/66 , G01R31/28
CPC分类号： H01L29/00 , G01R31/2818 , G01R31/2856 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test.
摘要翻译：提供一种包括半导体器件中的光激活测试连接的测试电路。在半导体器件的测试期间，光激发测试连接是导电的，并且在测试之后是非导电的。

10. 发明授权

US09383767B2 Circuit design for balanced logic stress 有权
公开(公告)号：US09383767B2
公开(公告)日：2016-07-05
申请号：US14280782
申请日：2014-05-19
申请人： International Business Machines Corporation
发明人： Nathaniel R. Chadwick , Frances S. M. Clougherty , William P. Hovis , Kirk D. Peterson , Mack W. Riley
IPC分类号： G06F1/08 , G06F13/20
CPC分类号： G06F1/08 , G06F13/20
摘要： An electronic system is disclosed, which may include a phase pipeline, a data pipeline, an input phase selector, and an output phase selector. The phase pipeline may have latches clocked by a clock signal, and designed to propagate phase signals from a phase input to a phase output. The data pipeline may have latches clocked by the phase pipeline clock signal, and designed to propagate data from a data input to a data output. The input phase selector may be designed to provide an inverted or a non-inverted copy of data from a data input, in response to a value at the phase input, to the data pipeline data input. The output phase selector may be designed to provide an inverted or a non-inverted copy of data from the data pipeline output to an output phase selector data output, in response to a phase pipeline output value.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式