专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08850378B2 Hierarchical design of integrated circuits with multi-patterning requirements 有权
标题翻译：具有多图案化要求的集成电路的分层设计
公开(公告)号：US08850378B2
公开(公告)日：2014-09-30
申请号：US13665276
申请日：2012-10-31
申请人： International Business Machines Corporation
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5009 , G06F17/5068 , G06F17/5081
摘要： Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.
摘要翻译：描述了用于避免在具有多图案化要求的集成电路的分层设计中对单元布置的限制的系统和方法。该方法可以在具有计算机可执行代码的计算机可执行代码中实现，该计算机可执行代码有形地体现在具有可编程指令的计算机可读存储介质上，该程序指令可操作以将颜色分配给第一单元中的每个图案形状，为第二单元中的每个图案形状分配颜色，表征第一单元格中每个图案形状的感兴趣量，确定在第一单元格中分配的颜色与第二单元格中分配的颜色可以一一对应，表征第二单元格中每个图案形状的感兴趣量使用针对第一小区表征的兴趣量，并对第一小区和第二小区的兴趣量进行建模。

2. 发明授权

US08949765B2 Modeling multi-patterning variability with statistical timing 有权
标题翻译：用统计时序建模多图案变异
公开(公告)号：US08949765B2
公开(公告)日：2015-02-03
申请号：US14139004
申请日：2013-12-23
申请人： International Business Machines Corporation
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/08 , G06F2217/10 , G06F2217/12 , G06F2217/84
摘要： Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.
摘要翻译：描述了在IC制造期间利用统计时序分析建模多图案变化的系统和方法。该方法可以被提供在具有计算机可执行代码的计算机基础结构中，计算机可执行代码有形地体现在具有可编程指令的计算机可读存储介质上，该程序指令可操作以限定集成电路设计中的至少所述编程指令进一步可操作以将集成电路设计的至少一个级别中的至少两个模式的所述至少一个变化源建模为至少两个变异性源。

3. 发明授权

US08832625B2 Systems and methods for correlated parameters in statistical static timing analysis 有权
公开(公告)号：US08832625B2
公开(公告)日：2014-09-09
申请号：US13780413
申请日：2013-02-28
申请人： International Business Machines Corporation
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081
摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

4. 发明申请

US20180096089A1 INTEGRATING MANUFACTURING FEEDBACK INTO INTEGRATED CIRCUIT STRUCTURE DESIGN 审中-公开
公开(公告)号：US20180096089A1
公开(公告)日：2018-04-05
申请号：US15810184
申请日：2017-11-13
申请人： International Business Machines Corporation
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/84
摘要： Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

5. 发明授权

US09171124B2 Parasitic extraction in an integrated circuit with multi-patterning requirements 有权
标题翻译：具有多图案化要求的集成电路中的寄生提取
公开(公告)号：US09171124B2
公开(公告)日：2015-10-27
申请号：US14139023
申请日：2013-12-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/82
摘要： Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation. The method further includes generating as output the statistical parasitics in at least one of a vector form and a collapsed reduced vector form.
摘要翻译：提供了用于在具有多图案化要求的集成电路的设计中提取寄生效应的系统和方法。该方法包括确定电阻解和电容解。该方法还包括执行电阻解和电容解的寄生提取以产生电阻解和电容解的平均值。该方法还包括在寄生提取期间捕获每个电阻解决方案和电容解的多图案变化源。该方法还包括确定每个捕获的变化源与相应的参数矢量的灵敏度。该方法还包括通过将每个电阻解和电容解乘以每个相应捕获的变化源的灵敏度来确定统计寄生效应。该方法还包括以矢量形式和折叠缩小矢量形式中的至少一个生成统计寄生效应作为输出。

6. 发明授权

US09378328B2 Modeling multi-patterning variability with statistical timing 有权
公开(公告)号：US09378328B2
公开(公告)日：2016-06-28
申请号：US14552782
申请日：2014-11-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/08 , G06F2217/10 , G06F2217/12 , G06F2217/84
摘要： Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.

7. 发明授权

US09104834B2 Systems and methods for single cell product path delay analysis 有权
标题翻译：单细胞产品路径延迟分析的系统和方法
公开(公告)号：US09104834B2
公开(公告)日：2015-08-11
申请号：US14514919
申请日：2014-10-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Brian A. Worth , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5031
摘要： Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.
摘要翻译：提供了使用产品路径延迟分析来限定单个单元的方法和系统。一种方法包括使用来自初始测试站点的模型来设计产品。该方法还包括为产品上的一个或多个路径创建性能路径测试。该方法还包括测量产品的性能路径参数。该方法包括确定测量的性能路径参数与预测的性能路径参数匹配。

8. 发明授权

US08904329B2 Systems and methods for single cell product path delay analysis 有权
标题翻译：单细胞产品路径延迟分析的系统和方法
公开(公告)号：US08904329B2
公开(公告)日：2014-12-02
申请号：US13735392
申请日：2013-01-07
申请人： International Business Machines Corporation
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , Brian A. Worth , Jinjun Xiong
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5031
摘要： Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.
摘要翻译：提供了使用产品路径延迟分析来限定单个单元的方法和系统。一种方法包括使用来自初始测试站点的模型来设计产品。该方法还包括为产品上的一个或多个路径创建性能路径测试。该方法还包括测量产品的性能路径参数。该方法包括确定测量的性能路径参数与预测的性能路径参数匹配。

9. 发明授权

US08856709B2 Systems and methods for correlated parameters in statistical static timing analysis 有权
公开(公告)号：US08856709B2
公开(公告)日：2014-10-07
申请号：US14138935
申请日：2013-12-23
申请人： International Business Machines Corporation
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081
摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.

10. 发明授权

US08806402B2 Modeling multi-patterning variability with statistical timing 有权
标题翻译：用统计时序建模多图案变异
公开(公告)号：US08806402B2
公开(公告)日：2014-08-12
申请号：US13665466
申请日：2012-10-31
申请人： International Business Machines Corporation
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5072 , G06F2217/08 , G06F2217/10 , G06F2217/12 , G06F2217/84
摘要： Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively.
摘要翻译：描述了在IC制造期间利用统计时序分析建模多图案变化的系统和方法。该方法可以被提供在具有计算机可执行代码的计算机基础结构中，计算机可执行代码有形地体现在具有可编程指令的计算机可读存储介质上，该程序指令可操作以限定集成电路设计中的至少所述编程指令进一步可操作以将集成电路设计的至少一个级别中的至少两个模式的所述至少一个变化源建模为至少两个变异性源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式