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1. 发明申请

US20230128057A1 SYSTEMS, METHODS, AND DEVICES FOR EFFICIENT EXECUTION OF ARTIFICIAL NEURAL NETWORKS 有权
公开(公告)号：US20230128057A1
公开(公告)日：2023-04-27
申请号：US17965166
申请日：2022-10-13
申请人： Infineon Technologies AG
发明人： Muhammad Hassan , Konrad Walluszik , Juergen Schaefer
IPC分类号： G06N3/063 , G06F7/544
摘要： A system for executing an artificial neural network having a plurality of interconnected nodes, the system includes a memory storing weight values of the neural network. The memory can be configured to a store node value and a mask bit value for each of the plurality of nodes of the neural network. Further the system can include multiply and accumulate (MAC) units to perform operations for determining node values. The system includes a control unit circuitry that, during execution of the neural network, dynamically controls operations of the MAC units to cause a reduction in a number of calculations to be performed by the MAC units. The control unit circuitry causes the MAC units to perform operations involving a subset of the plurality of nodes to avoid performing operations involving nodes of the plurality nodes that are outside of the subset.

2. 发明授权

US11621717B1 Non-linear inter-ADC calibration by time equidistant triggering 有权
公开(公告)号：US11621717B1
公开(公告)日：2023-04-04
申请号：US17519759
申请日：2021-11-05
申请人： Infineon Technologies AG
发明人： Mihail Jefremow , Ralph Mueller-Eschenbach , Juergen Schaefer , Arndt Voigtlaender , David Zipperstein
IPC分类号： H03M1/10 , H03M1/50 , H03M1/46 , H03M1/12
摘要： A calibration circuit, including: a first analog-to-digital converter (ADC) configured to sample a nonlinear reference signal continuously at an equidistant sampling rate to generate a reference sampled signal; a trigger timer configured to generate trigger signals; a second ADC configured to sample a point of each of the nonlinear reference signal and repeated versions of the nonlinear reference signal in response to the respective trigger signals at equidistantly increasing delays, to generate a device-under-test (DUT) sampled voltage; and processing circuitry configured to estimate a differential nonlinearity (DNL) of the DUT sampled signal, estimate a DNL of the reference sampled signal, and compare the estimated DNL of the DUT sampled signal with the estimated DNL of the reference sampled signal, to generate a DNL performance indication signal of the second ADC.

3. 发明授权

US10087872B2 System and method for a synchronized driver circuit 有权
公开(公告)号：US10087872B2
公开(公告)日：2018-10-02
申请号：US14945087
申请日：2015-11-18
申请人： Infineon Technologies AG
发明人： Christian Schweikert , Gerhard Pichler , Marco Nicolo , Frank Auer , Guenther Mohr , Juergen Schaefer , Patrick Leteinturier
IPC分类号： H01H9/00 , F02D41/30 , F02D41/26 , F02M51/06 , H03K17/687 , F02D41/00 , F02D41/20 , F16C32/04 , F02D41/14
摘要： According to an embodiment, a controller system that is configured to drive a power switch includes a driver integrated circuit (IC), which includes an interface circuit, a synchronization circuit, and a drive circuit. The interface circuit is configured to receive a control scheme over a serial interface. The synchronization circuit is coupled to the interface circuit and is configured to receive an angular position signal and synchronize a drive signal with the angular position signal, where the drive signal is based on the control scheme. The drive circuit is coupled to the synchronization circuit and is configured to drive the power switch using the drive signal.

4. 发明授权

US09374081B2 Method for driving a load 有权
标题翻译：驾驶负载的方法
公开(公告)号：US09374081B2
公开(公告)日：2016-06-21
申请号：US13745516
申请日：2013-01-18
申请人： Infineon Technologies AG
发明人： Johannes Janschitz , Herwig Wappis , Juergen Schaefer
IPC分类号： H01H47/00 , H03K17/284 , H03K17/16
CPC分类号： H03K17/284 , H03K17/166
摘要： An electronic switch includes a load path connected in series with the load and a drive terminal for receiving a drive signal. The electronic switch is operable to switch between a first operation state and a second operation state dependent on the drive signal. In a first switching cycle, the electronic switch is switched from the first operation state to the second operation state and a voltage across the load is evaluated during the first switching cycle in order to obtain a measured switching profile. The measured switching profile is compared with a reference profile. A drive profile dependent on the comparison is provided. The drive profile is used to drive the electronic switch in a second switching cycle after the first switching cycle. At least two drive parameters are used at different times in the at least one second switching cycle to drive the electronic switch.
摘要翻译：电子开关包括与负载串联连接的负载路径和用于接收驱动信号的驱动端子。电子开关可操作以取决于驱动信号在第一操作状态和第二操作状态之间切换。在第一开关周期中，电子开关从第一操作状态切换到第二操作状态，并且在第一开关周期期间评估负载两端的电压，以获得测量的开关曲线。将测量的切换轮廓与参考轮廓进行比较。提供了依赖于比较的驱动器配置文件。驱动器配置文件用于在第一个开关周期之后的第二个开关周期中驱动电子开关。在至少一个第二切换周期中，在不同时间使用至少两个驱动参数来驱动电子开关。

5. 发明申请

US20220179012A1 IMPLEMENTATION TO DETECT FAILURE OR FAULT ON AN ANALOG INPUT PATH FOR SINGLE ANALOG INPUT FUNCTIONAL SAFETY APPLICATIONS 有权
公开(公告)号：US20220179012A1
公开(公告)日：2022-06-09
申请号：US17114915
申请日：2020-12-08
申请人： Infineon Technologies AG
发明人： Ketan Dewan , Rocco Calabro , Juergen Schaefer
IPC分类号： G01R31/54 , H03M1/12
摘要： An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

6. 发明申请

US20220166442A1 DEVICES AND SYSTEMS FOR ANALOG-TO-DIGITAL CONVERSION 有权
公开(公告)号：US20220166442A1
公开(公告)日：2022-05-26
申请号：US17533382
申请日：2021-11-23
申请人： Infineon Technologies AG
发明人： Ketan Dewan , Rocco Calabro , Juergen Schaefer , David Schaffenrath
IPC分类号： H03M1/38
摘要： An analog-to-digital device includes a sampling circuit for sampling an input signal. The sampling circuit stops sampling in response to obtaining a trigger signal. The analog-to-digital device includes an analog-to-digital converter circuit which includes an analog to digital converter (ADC) for converting a sampled input provided from the sampling circuit to digital output.

7. 发明授权

US11329608B1 Oscillator circuit with negative resistance margin testing 有权
公开(公告)号：US11329608B1
公开(公告)日：2022-05-10
申请号：US17078484
申请日：2020-10-23
申请人： Infineon Technologies AG
发明人： Mihail Jefremow , Rex Kho , Ralph Mueller-Eschenbach , Juergen Schaefer , Arndt Voigtlaender , Wei Wang
IPC分类号： H03B5/36 , H03B7/06
摘要： Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.

8. 发明申请

US20220085824A1 TIME MEASUREMENT OF A CLOCK-BASED SIGNAL 有权
公开(公告)号：US20220085824A1
公开(公告)日：2022-03-17
申请号：US17467767
申请日：2021-09-07
申请人： Infineon Technologies AG
发明人： Mihail Jefremow , Ketan Dewan , Rex Kho , Ralph Mueller-Eschenbach , Juergen Schaefer
IPC分类号： H03M1/12 , G06F1/10 , G01R31/317
摘要： A device is provided for time measurement of a clock-based signal comprising a sample stage comprising a switching device that is driven by a control signal and a capacitance (Cs), wherein the sample stage is arranged to transform an analog input signal in an analog output signal, the device further comprising an analog-to-digital converter to convert the analog output signal into a digital output signal, wherein the input signal applied to the sample stage is a reference signal and wherein the clock-based signal is applied to the control signal. Also, an according method is suggested.

9. 发明申请

US20210382776A1 FAULT CHECK WITHOUT SOFTWARE INTERVENTION 有权
公开(公告)号：US20210382776A1
公开(公告)日：2021-12-09
申请号：US16891312
申请日：2020-06-03
申请人： Infineon Technologies AG
发明人： Ketan Dewan , Juergen Schaefer
IPC分类号： G06F11/07 , G08B21/18 , B60W50/02 , H04L12/40
摘要： A fault check circuit, including a first channel comparator to output a first channel comparator output signal indicating whether a first channel digital signal is outside of a first channel threshold range, wherein the first channel digital signal is A/D converted from a first channel analog signal; a second channel comparator to output a second channel comparator output signal indicating whether a second channel digital signal is outside of a second channel threshold range, wherein the second channel digital signal is A/D converted from a second channel analog signal; and an alarm generator circuit to combine the first and second channel comparator output signals, and output a fault check signal, wherein the first and second channel comparators and the alarm generator circuit are implemented in hardware, and the fault check circuit performs a fault check without software intervention.

10. 发明授权

US10198332B2 System on chip integrity verification method and system 有权
公开(公告)号：US10198332B2
公开(公告)日：2019-02-05
申请号：US15288434
申请日：2016-10-07
申请人： Infineon Technologies AG
发明人： Varun Kumar , Sandeep Naduvalamane , Sumit Khandelwal , Puneetha Mukherjee , Juergen Schaefer
IPC分类号： G06F11/00 , G06F11/22 , G06F9/4401 , G06F9/445 , G06F11/27 , G06F15/78
摘要： Methods and systems for checking the integrity of a system on chip (SOC) are described. The SOC can include a controller and one or more registers. Register value(s) from the register(s) can be obtained at a first time to generate a first set of register values. Process(es) of the SOC are executed at a second time after the first time. Register values can again be obtained from the registers at a third time after the second time to generate a second set of register values. The first set of register values can be compared with the second set of register values. Based on the comparison, an operating mode of the SOC can be adjusted. The SOC integrity verification system and method can be used in safety and/or monitoring application(s), such as ASIL applications. For example, the system and method can be used in partial or fully autonomous (self-driving) automotive systems.

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