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1. 发明申请

US20150255136A1 Symmetrical Differential Sensing Method and System for STT MRAM 审中-公开
标题翻译： STT MRAM对称差分传感方法及系统
公开(公告)号：US20150255136A1
公开(公告)日：2015-09-10
申请号：US14714796
申请日：2015-05-18
申请人： Infineon Technologies AG
发明人： David Mueller , Wolf Allers , Mihail Jefremow
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C7/02 , G11C7/12 , G11C11/16 , G11C11/1659 , G11C29/021 , G11C29/028 , G11C2029/5006
摘要： The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In one example, a system for reading a memory cell includes a sense path and an inverse path. A reference current is provided through the sense path and is sampled via a first sampling element in the sense path, and a cell current from the memory cell is provided through the inverse sense path and is sampled via a second sampling element in the inverse sense path. Subsequently, the memory cell is disconnected from the inverse sense path, the cell current is provided through the sense path, the reference source is disconnected from the sense path, and the reference current is provided through the inverse sense path. The output levels are then determined by the cell and reference currents working against the sampled reference and sampled cell currents.
摘要翻译：本发明涉及用于读取存储器单元，特别是STT MRAM的方法和系统。在一个示例中，用于读取存储器单元的系统包括感测路径和反向路径。通过感测路径提供参考电流，并且通过感测路径中的第一采样元件进行采样，并且通过反向感测路径提供来自存储器单元的单元电流，并且经由反向感测路径中的第二采样元件进行采样。随后，存储器单元与反向感测路径断开，通过感测路径提供单元电流，参考源与感测路径断开，并通过反向感测路径提供参考电流。然后，输出电平由电池和参考电流根据采样的参考和采样单元电流工作来确定。

2. 发明授权

US11621717B1 Non-linear inter-ADC calibration by time equidistant triggering 有权
公开(公告)号：US11621717B1
公开(公告)日：2023-04-04
申请号：US17519759
申请日：2021-11-05
申请人： Infineon Technologies AG
发明人： Mihail Jefremow , Ralph Mueller-Eschenbach , Juergen Schaefer , Arndt Voigtlaender , David Zipperstein
IPC分类号： H03M1/10 , H03M1/50 , H03M1/46 , H03M1/12
摘要： A calibration circuit, including: a first analog-to-digital converter (ADC) configured to sample a nonlinear reference signal continuously at an equidistant sampling rate to generate a reference sampled signal; a trigger timer configured to generate trigger signals; a second ADC configured to sample a point of each of the nonlinear reference signal and repeated versions of the nonlinear reference signal in response to the respective trigger signals at equidistantly increasing delays, to generate a device-under-test (DUT) sampled voltage; and processing circuitry configured to estimate a differential nonlinearity (DNL) of the DUT sampled signal, estimate a DNL of the reference sampled signal, and compare the estimated DNL of the DUT sampled signal with the estimated DNL of the reference sampled signal, to generate a DNL performance indication signal of the second ADC.

3. 发明申请

US20140215124A1 SYSTEM AND METHOD FOR ADAPTIVE BIT RATE PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：用于存储器件的自适应位速率编程的系统和方法
公开(公告)号：US20140215124A1
公开(公告)日：2014-07-31
申请号：US13751883
申请日：2013-01-28
申请人： INFINEON TECHNOLOGIES AG
发明人： Wolf Allers , Jan Otterstedt , Mihail Jefremow , Edvin Paparisto , Leonardo Castro
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C16/06 , G11C16/10 , G11C16/24 , G11C16/3486
摘要： The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.
摘要翻译：本公开涉及电子存储器系统，更具体地，涉及用于存储器件的自适应比特率编程的系统，以及用于存储器件的自适应比特率编程的方法。根据实施例，提供了一种用于包括多个存储器单元的存储器件的自适应位速率编程的系统，其中存储器单元被配置为可通过施加由电流源提供的电流进行电可编程，所述系统包括选择用于基于来自当前源的电流的可用性来选择用于编程的存储器单元的设备。

4. 发明授权

US11177987B1 Resolver signal processing 有权
公开(公告)号：US11177987B1
公开(公告)日：2021-11-16
申请号：US17081433
申请日：2020-10-27
申请人： Infineon Technologies AG
发明人： Mihail Jefremow , Michael Augustin , Ketan Dewan , Ralph Mueller-Eschenbach , Juergen Schaefer
IPC分类号： H04L5/12 , H04L23/02 , H04L27/06 , H04L27/08 , H03M1/64 , H04L27/00
摘要： Processing a resolver signal by a microcontroller includes generating, by a carrier signal generator, a carrier signal for output to a resolver; receiving modulated carrier signals from a resolver via hardware that is external to the microcontroller; integrating, by an integrator, respective integrator input signals which are based on the modulated carrier signals, to generate respective envelope signals, wherein a start of an integration window of the integrator is set with respect to a start of the carrier signal; and determining an angular position sensed by the resolver based on the envelope signals.

5. 发明授权

US10236041B2 Determining a state of a memory cell 有权
公开(公告)号：US10236041B2
公开(公告)日：2019-03-19
申请号：US15597846
申请日：2017-05-17
申请人： Infineon Technologies AG
发明人： Mihail Jefremow , Thomas Kern , Christian Peters
IPC分类号： G11C7/22 , G11C7/06 , G11C13/00 , G11C16/26 , G11C16/28 , G11C16/32
摘要： A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.

6. 发明申请

US20180190333A1 DETERMINING A STATE OF A MEMORY CELL 审中-公开
公开(公告)号：US20180190333A1
公开(公告)日：2018-07-05
申请号：US15597846
申请日：2017-05-17
申请人： Infineon Technologies AG
发明人： Mihail Jefremow , Thomas Kern , Christian Peters
IPC分类号： G11C7/22 , G11C7/06
CPC分类号： G11C7/22 , G11C7/06 , G11C7/065 , G11C7/067 , G11C13/004 , G11C13/0061 , G11C16/26 , G11C16/28 , G11C16/32 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2207/063 , G11C2207/068 , G11C2213/79
摘要： A method is suggested for determining a state of a memory cell via a sense amplifier the method including applying a first signal to the sense amplifier; sensing a first response; determining a reference signal based on the first signal; sensing a second response based on a second signal that is determined based on the first signal; and determining the state of the memory cell based on the second response and the reference signal. Also, a memory device that is able to determine the state of the memory cell is provided.

7. 发明授权

US09460759B2 Sense amplifier of a memory cell 有权
标题翻译：存储单元的感应放大器
公开(公告)号：US09460759B2
公开(公告)日：2016-10-04
申请号：US14149353
申请日：2014-01-07
申请人： Infineon Technologies AG
发明人： Thomas Kern , Mihail Jefremow
IPC分类号： G11C7/12 , G11C7/06 , G11C11/16 , G11C13/00 , G11C16/26
CPC分类号： G11C7/062 , G11C7/12 , G11C11/1673 , G11C11/1693 , G11C13/004 , G11C16/26
摘要： A sense amplifier of a memory cell having a sense voltage generating circuit configured to generate a sense voltage; and a sensing circuit configured to compare a bitline voltage of the memory cell with the sense voltage, and to output a digital output signal indicating a content of the memory cell, wherein during a sense phase, the sensing circuit is decoupled from a voltage supply which charges a bitline capacitance during a precharge phase, and is coupled to and supplied by the bitline capacitance. The sense voltage generating circuit may be further configured to generate a sense voltage that during a precharge phase is dependent on the voltage supply and during a sense phase is independent of the voltage supply.
摘要翻译：具有感测电压发生电路的存储单元的读出放大器被配置为产生检测电压; 以及感测电路，被配置为将存储器单元的位线电压与感测电压进行比较，并且输出指示存储器单元的内容的数字输出信号，其中在感测阶段期间，感测电路与电压源在预充电阶段期间对位线电容充电，并且被位线电容耦合并由位线电容提供。感测电压产生电路还可以被配置为产生在预充电阶段期间取决于电压供应并且在感测阶段期间独立于电压供应的感测电压。

8. 发明授权

US09196320B2 Method, apparatus and device for data processing 有权
标题翻译：用于数据处理的方法，装置和装置
公开(公告)号：US09196320B2
公开(公告)日：2015-11-24
申请号：US14106277
申请日：2013-12-13
申请人： Infineon Technologies AG
发明人： Thomas Kern , Mihail Jefremow
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/1069 , G11C11/1673 , G11C11/1693 , G11C13/004 , G11C16/28 , G11C2013/0042
摘要： An embodiment relates to a method for data processing and comprises determining an electrical variable for each cell of a data bit, transforming each electrical variable into the time domain, and determining a blank state for at least one data bit based on a comparison of the transformed electrical variables.
摘要翻译：一个实施例涉及一种用于数据处理的方法，包括：确定数据位的每个单元的电变量，将每个电变量变换成时域，以及根据变换后的变量的比较确定至少一个数据位的空白状态电气变量。

9. 发明申请

US20220399886A1 ELECTRONIC DEVICE 有权
公开(公告)号：US20220399886A1
公开(公告)日：2022-12-15
申请号：US17836181
申请日：2022-06-09
申请人： Infineon Technologies AG
发明人： Mihail Jefremow , David Zipperstein , Juergen Schaefer , Holger Dienst , Markus Bichl , Ralph Mueller-Eschenbach , Arndt Voigtlaender
IPC分类号： H03K17/56 , H03M3/00
摘要： According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.

10. 发明申请

US20220131499A1 OSCILLATOR CIRCUIT WITH NEGATIVE RESISTANCE MARGIN TESTING 有权
公开(公告)号：US20220131499A1
公开(公告)日：2022-04-28
申请号：US17078484
申请日：2020-10-23
申请人： Infineon Technologies AG
发明人： Mihail Jefremow , Rex Kho , Ralph Mueller-Eschenbach , Juergen Schaefer , Arndt Voigtlaender , Wei Wang
IPC分类号： H03B7/06 , H03B5/36
摘要： Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.

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