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1. 发明申请

US20160181380A1 Semiconductor Device Metal-Insulator-Semiconductor Contacts with Interface Layers and Methods for Forming the Same 审中-公开
标题翻译：半导体器件金属绝缘体 - 具有界面层的半导体触点及其形成方法
公开(公告)号：US20160181380A1
公开(公告)日：2016-06-23
申请号：US14576597
申请日：2014-12-19
申请人： Intermolecular Inc. , Global Foundries, Inc.
发明人： Amol Joshi , Sean Barstow , Paul Besser , Ashish Bodke , Guillaume Bouche , Nobumichi Fuchigami , Zhendong Hong , Shaoming Koh , Albert Sanghyup Lee , Salil Mujumdar , Abhijit Pethe , Mark Victor Raymond
IPC分类号： H01L29/417 , H01L21/285 , H01L29/66 , H01L21/02 , H01L29/45 , H01L29/78
CPC分类号： H01L21/28568 , H01L21/02186 , H01L21/02362 , H01L21/28512 , H01L21/76831 , H01L21/76843 , H01L29/47 , H01L29/66643 , H01L29/78 , H01L29/7839
摘要： Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. A source region and a drain region are formed on the semiconductor substrate. A gate electrode is formed between the source region and the drain region. A contact is formed above at least one of the source region and the drain region. The contact includes an insulating layer formed above the semiconductor substrate, an interface layer formed above the insulating layer, and a metallic layer formed above the interface layer. The interface layer is operable as a barrier between a material of the insulating layer and a material of the metallic layer, reduces the electrical resistance between the material of the insulating layer and the material of the metallic layer, or a combination thereof.
摘要翻译：本文提供的实施例描述了用于形成半导体器件的系统和方法。提供半导体衬底。源极区和漏极区形成在半导体衬底上。在源极区域和漏极区域之间形成栅电极。在源极区域和漏极区域中的至少一个上方形成接触。触点包括形成在半导体衬底之上的绝缘层，形成在绝缘层之上的界面层以及形成在界面层之上的金属层。界面层可用作绝缘层的材料和金属层的材料之间的屏障，减小了绝缘层的材料与金属层的材料之间的电阻或其组合。

2. 发明申请

US20150311206A1 METHODS OF FORMING GATE STRUCTURES FOR TRANSISTOR DEVICES FOR CMOS APPLICATIONS AND THE RESULTING PRODUCTS 有权
标题翻译：用于CMOS应用和结果产品的晶体管器件的门结构的方法
公开(公告)号：US20150311206A1
公开(公告)日：2015-10-29
申请号：US14793005
申请日：2015-07-07
申请人： GLOBAL FOUNDRIES Inc.
发明人： Zhendong Hong , Susie Tzeng , Amol Joshi , Ashish Bodke , Divya Pisharoty , Usha Raghuram , Olov Karlsson , Kisik Choi , Salil Mujumdar , Paul R. Besser , Jinping Liu , Hoon Kim
IPC分类号： H01L27/092 , H01L29/51 , H01L29/49
CPC分类号： H01L27/0922 , H01L21/28097 , H01L21/28185 , H01L21/28194 , H01L21/823835 , H01L27/092 , H01L29/4975 , H01L29/517 , H01L29/66545
摘要： An integrated circuit product includes an NMOS transistor having a gate structure that includes an NMOS gate insulation layer, a first NMOS metal layer positioned on the NMOS gate insulation layer, an NMOS metal silicide material positioned above the first NMOS metal layer, and a layer of a second metal material positioned above and in contact with the NMOS gate insulation layer, the first NMOS metal layer, and the NMOS metal silicide layer. The PMOS transistor has a gate structure that includes a PMOS gate insulation layer, a first PMOS metal layer positioned on the PMOS gate insulation layer, a PMOS metal silicide material positioned above the first PMOS metal layer, and a layer of the second metal material positioned above and in contact with the PMOS gate insulation layer, the first PMOS metal layer, and the PMOS metal silicide layer.
摘要翻译：集成电路产品包括具有栅极结构的NMOS晶体管，该栅极结构包括NMOS栅绝缘层，位于NMOS栅绝缘层上的第一NMOS金属层，位于第一NMOS金属层上方的NMOS金属硅化物材料，位于NMOS栅极绝缘层上方并与NMOS栅绝缘层接触的第二金属材料，第一NMOS金属层和NMOS金属硅化物层。 PMOS晶体管具有栅极结构，其包括PMOS栅极绝缘层，位于PMOS栅极绝缘层上的第一PMOS金属层，位于第一PMOS金属层上方的PMOS金属硅化物材料和位于第一PMOS金属层上方的第二金属材料层并且与PMOS栅绝缘层，第一PMOS金属层和PMOS金属硅化物层接触。

3. 发明授权

US08685829B1 Method for forming MOS capacitor 失效
标题翻译：形成MOS电容的方法
公开(公告)号：US08685829B1
公开(公告)日：2014-04-01
申请号：US13706680
申请日：2012-12-06
申请人： Intermolecular Inc.
发明人： Amol Joshi
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L29/94
摘要： A method of processing a substrate is provided. The method includes forming a first oxide layer on the substrate and patterning the first oxide layer utilizing a lithography process, the patterning defining a plurality of active areas on the substrate. The method includes forming a second oxide layer in each active area and forming a plurality of metal electrodes over the second oxide layer through a shadow mask technique, wherein the shadow mask technique is performed without alignment to an active area.
摘要翻译：提供了一种处理衬底的方法。该方法包括在衬底上形成第一氧化物层并利用光刻工艺对第一氧化物层进行构图，所述图案化在衬底上限定多个有源区。该方法包括在每个有源区域中形成第二氧化物层，并通过荫罩技术在第二氧化物层上形成多个金属电极，其中在与有源区域对准的情况下进行荫罩技术。

4. 发明申请

US20150187664A1 High Productivity Combinatorial Testing of Multiple Work Function Materials on the Same Semiconductor Substrate 审中-公开
标题翻译：多功能材料在同一半导体基板上的高效率组合测试
公开(公告)号：US20150187664A1
公开(公告)日：2015-07-02
申请号：US14140727
申请日：2013-12-26
申请人： Intermolecular Inc.
发明人： Amol Joshi
IPC分类号： H01L21/66 , H01L21/28
CPC分类号： H01L22/14 , H01L21/28026 , H01L22/20
摘要： Provided are methods of high productivity combinatorial (HPC) screening of work function materials. Multiple test materials may be deposited as separate blanket layers on the same substrate while still forming individual interfaces with a common base layer. The thickness of each test material layer ensures that its work function properties are not impacted when other layers are deposited over that layer. A method may involve depositing a blocking layer over the base layer and selectively removing the blocking layer from a first site isolated region. A first test material is then deposited as a blanket layer and forms an interface with the base layer in that first region only. The first test material layer and the blocking layer are selectively removed from a second site isolated region followed by depositing a second test material layer as another blanket layer, which forms an interface with the base layer in the second region only.
摘要翻译：提供了工作功能材料的高生产率组合（HPC）筛选方法。多个测试材料可以作为单独的覆盖层沉积在同一衬底上，同时仍然与公共基底层形成单独的界面。每个测试材料层的厚度确保当其它层沉积在该层上时，其功函数特性不受影响。一种方法可以包括在基底层上沉积阻挡层，并从第一位置隔离区选择性地去除阻挡层。然后将第一测试材料沉积为覆盖层，并且仅在该第一区域中与基底层形成界面。第一测试材料层和阻挡层从第二位置分离区域选择性地去除，随后沉积作为另一覆盖层的第二测试材料层，其仅与第二区域中的基层形成界面。

5. 发明申请

US20140179100A1 Method to Control Depth Profiles of Dopants Using a Remote Plasma Source 有权
标题翻译：使用远程等离子体源控制掺杂剂深度分布的方法
公开(公告)号：US20140179100A1
公开(公告)日：2014-06-26
申请号：US13726972
申请日：2012-12-26
申请人： INTERMOLECULAR, INC.
发明人： Sandip Niyogi , Amol Joshi , Chi-I Lang , Salil Mujumdar
IPC分类号： H01L21/02 , H01L21/768
CPC分类号： H01L21/76886 , C23C14/5826 , C23C16/45536 , H01J37/32357 , H01L21/02181 , H01L21/022 , H01L21/02323 , H01L21/02332 , H01L21/0234 , H01L21/28088 , H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3215 , H01L21/67207 , H01L21/68764 , H01L21/68792 , H01L29/517 , H01L29/665 , H01L29/6653
摘要： Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.
摘要翻译：公开了使用远程等离子体源的处理方法和装置。该装置包括封闭衬底支撑件，远程等离子体源和喷头的外室。基板加热器可以安装在基板支撑件中。运输系统移动基板支撑件并且能够定位基板。远程等离子体源可用于提供等离子体表面处理或作为将掺杂剂掺入预沉积层的源。

6. 发明申请

US20160093711A1 Tantalum carbide metal gate stack for mid-gap work function applications 审中-公开
标题翻译：用于中间隙功能应用的钽硬质合金金属栅极叠层
公开(公告)号：US20160093711A1
公开(公告)日：2016-03-31
申请号：US14315079
申请日：2014-06-25
申请人： Intermolecular Inc. , GLOBALFOUNDRIES, Inc.
发明人： Zhendong Hong , Paul Besser , Kisik Choi , Amol Joshi , Olov Karlsson , Susie Tzeng
IPC分类号： H01L29/49 , H01L21/285 , H01L29/423 , H01L21/28
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28185 , H01L29/513 , H01L29/517 , H01L29/66795 , H01L29/785
摘要： Devices with lightly-doped semiconductor channels (e.g., FinFETs) need mid-gap (˜4.6-4.7 eV) work-function layers, preferably with low resistivity and a wide process window, in the gate stack. Tantalum carbide (TaC) has a mid-gap work function that is insensitive to thickness. TaC can be deposited with good adhesion on high-k materials or on optional metal-nitride cap layers. TaC can also serve as the fill metal, or it can be used with other fills such as tungsten (W) or aluminum (Al). The TaC may be sputtered from a TaC target, deposited by ALD or CVD using TaCl4 and TMA, or produced by methane treatment of deposited Ta. Al may be added to tune the threshold voltage.
摘要翻译：具有轻掺杂半导体通道（例如，FinFET）的器件在栅极堆叠中需要中间隙（〜4.6-6.7eV）的功函数层，优选地具有低电阻率和宽的工艺窗口。碳化钽（TaC）具有对厚度不敏感的中间间隙功能。可以在高k材料或任选的金属氮化物盖层上沉积具有良好粘附性的TaC。 TaC也可以作为填充金属，也可以与钨（W）或铝（Al）等其他填料一起使用。 TaC可以从TaC靶溅射，通过ALD或CVD使用TaCl4和TMA沉积，或通过沉积的Ta的甲烷处理产生。可以添加Al来调节阈值电压。

7. 发明申请

US20150140838A1 Two Step Deposition of High-k Gate Dielectric Materials 审中-公开
标题翻译：高k栅介质材料的两步沉积
公开(公告)号：US20150140838A1
公开(公告)日：2015-05-21
申请号：US14083761
申请日：2013-11-19
申请人： Intermolecular Inc.
发明人： Kevin Kashefi , Amol Joshi , Salil Mujumdar
IPC分类号： H01L29/51 , H01L21/02 , H01L21/28
CPC分类号： H01L29/517 , C23C16/405 , C23C16/45527 , C23C16/56 , H01L21/02181 , H01L21/022 , H01L21/0228 , H01L21/02318 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/665 , H01L29/6659
摘要： Methods and apparatus for forming a dielectric layer for use as a gate dielectric are provided. A high-k layer is formed with first ALD process using a halogen-based precursor. The metal in the halogen-based precursor may be at least one of hafnium, zirconium, or titanium. The halogen in the halogen-based precursor may be at least one of fluorine, chlorine, or iodine. In some embodiments, the halogen-based metal precursor includes hafnium chloride. The remainder of the high-k layer is formed with second ALD process using a metal organic-based precursor. The metal in the metal organic-based precursor may be at least one of hafnium, zirconium, or titanium. The organic ligands in the metal organic-based precursor may be at least one of β-diketonate precursors, alkoxide precursors, amino precursors. In some embodiments, the metal organic-based precursor includes amino precursors.
摘要翻译：提供了形成用作栅极电介质的电介质层的方法和装置。使用卤素前体的第一ALD工艺形成高k层。卤素前体中的金属可以是铪，锆或钛中的至少一种。卤素前体中的卤素可以是氟，氯或碘中的至少一种。在一些实施方案中，卤素基金属前体包括氯化铪。高k层的其余部分由使用金属有机基前体的第二ALD工艺形成。金属有机基前体中的金属可以是铪，锆或钛中的至少一种。金属有机基前体中的有机配体可以是β-二酮前体，醇盐前体，氨基前体中的至少一种。在一些实施方案中，金属有机基前体包括氨基前体。

8. 发明申请

US20150064361A1 UV treatment for ALD film densification 审中-公开
标题翻译：紫外线治疗ALD膜致密化
公开(公告)号：US20150064361A1
公开(公告)日：2015-03-05
申请号：US14018112
申请日：2013-09-04
申请人： Intermolecular Inc.
发明人： Frank Greer , Amol Joshi , Kevin Kashefi
IPC分类号： B05D3/06
CPC分类号： C23C16/45536 , C23C16/45527
摘要： Irradiation with ultraviolet (UV) light during atomic layer deposition (ALD) can be used to cleave unwanted bonds on the layer being formed (e.g., trapped precursor ligands or process-gas molecules). Alternatively, the UV irradiation can be used to excite the targeted bonds so they may be more easily cleaved by other means. The use of UV may enable the formation of low-defect-density films at lower deposition temperatures (e.g.,
摘要翻译：可以使用在原子层沉积（ALD）期间用紫外线（UV）光照射在所形成的层（例如，捕获的前体配体或工艺气体分子）上切割不需要的键。或者，可以使用UV照射来激发目标键，使得它们可以通过其它方式更容易地被切割。使用UV可以在较低的沉积温度（例如<250℃）下形成低缺陷密度的膜，或者减少对高温后沉积退火的需要，从而提高在热处理后形成的器件的质量，敏感材料如锗。

9. 发明申请

US20150118828A1 Reduction of native oxides by annealing in reducing gas or plasma 有权
标题翻译：还原气体或等离子体中还原天然氧化物
公开(公告)号：US20150118828A1
公开(公告)日：2015-04-30
申请号：US14068906
申请日：2013-10-31
申请人： Intermolecular Inc.
发明人： Frank Greer , Amol Joshi , Kevin Kashefi , Albert Sanghyup Lee , Abhijit Pethe , J Watanabe
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L21/28158 , C23C16/0218 , C23C16/45525 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/28238
摘要： Native oxide growth on germanium, silicon germanium, and InGaAs undesirably affects CET (capacitive equivalent thickness) and EOT (effective oxide thickness) of high-k and low-k metal-oxide layers formed on these semiconductors. Even if pre-existing native oxide is initially removed from the bare semiconductor surface, some metal oxide layers are oxygen-permeable in thicknesses below about 25 Å thick. Oxygen-containing species used in the metal-oxide deposition process may diffuse through these permeable layers, react with the underlying semiconductor, and re-grow the native oxide. To eliminate or mitigate this re-growth, the substrate is exposed to a gas or plasma reductant (e.g., containing hydrogen). The reductant diffuses through the permeable layers to react with the re-grown native oxide, detaching the oxygen and leaving the un-oxidized semiconductor. The reduction product(s) resulting from the reaction may then be removed from the substrate (e.g., driven off by heat).
摘要翻译：在锗，硅锗和InGaAs上的天然氧化物生长不利地影响在这些半导体上形成的高k和低k金属氧化物层的CET（电容等效厚度）和EOT（有效氧化物厚度）。即使预先存在的原生氧化物最初从裸露的半导体表面去除，一些金属氧化物层的厚度可以在大约25埃的厚度下透氧。在金属氧化物沉积工艺中使用的含氧物质可以扩散通过这些可渗透层，与下面的半导体反应，并重新生长天然氧化物。为了消除或减轻这种再生长，将基底暴露于气体或等离子体还原剂（例如含有氢气）中。还原剂通过可渗透层扩散以与再生的天然氧化物反应，分离氧并留下未氧化的半导体。然后可以从反应物中除去由反应产生的还原产物（例如，通过加热驱除）。

10. 发明申请

US20140099785A1 Sacrificial Low Work Function Cap Layer 审中-公开
标题翻译：牺牲低功能帽层
公开(公告)号：US20140099785A1
公开(公告)日：2014-04-10
申请号：US13645259
申请日：2012-10-04
申请人： INTERMOLECULAR, INC.
发明人： Salil Mujumdar , Amol Joshi
IPC分类号： H01L21/02
CPC分类号： H01L21/02697 , H01L21/28185 , H01L21/28194 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A method includes forming an interlayer on a substrate, depositing a dielectric on the interlayer to form a dielectric stack, forming a sacrificial cap layer over the dielectric stack, processing the substrate to alter properties of the dielectric stack, and removing the sacrificial cap layer.
摘要翻译：一种方法包括在衬底上形成中间层，在中间层上沉积电介质以形成电介质叠层，在电介质叠层上形成牺牲覆盖层，处理衬底以改变电介质层的性质，以及去除牺牲覆盖层。

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