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1. 发明授权

US09209948B2 Testing a decision feedback equalizer (‘DFE’) 有权
标题翻译：测试反馈均衡器（'DFE'）
公开(公告)号：US09209948B2
公开(公告)日：2015-12-08
申请号：US14599605
申请日：2015-01-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eugene R. Atwood , Matthew B. Baecher , Minhan Chen , Hayden C. Cranford, Jr. , William R. Kelly , Todd M. Rasmus
IPC分类号： H04B17/00 , H04L1/24 , H04L25/03 , H04B17/20
CPC分类号： H04L1/244 , H04B17/00 , H04B17/20 , H04L25/03057 , H04L25/03248
摘要： Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
摘要翻译：测试判决反馈均衡器（DFE），DFE包括可操作地耦合到多个锁存器的加法放大器和用于接收数据信号的输入信号线，包括：防止差分数据信号被加法放大器接收; 并对每个要测试的水龙头进行迭代：将每个水龙头的抽头系数设置为零; 将所述多个锁存器的输出设置为预定值; 将要测试的水龙头的抽头系数设置为满量程值; 以及确定来自所述DFE的合成输出信号是否与预定的预期输出信号匹配。

2. 发明申请

US20180059138A1 SEMICONDUCTOR MICRO PROBE ARRAY HAVING COMPLIANCE 审中-公开
公开(公告)号：US20180059138A1
公开(公告)日：2018-03-01
申请号：US15252301
申请日：2016-08-31
申请人： International Business Machines Corporation
发明人： Eugene R. Atwood
IPC分类号： G01R1/067
CPC分类号： G01R1/06716 , G01R1/0735 , G01R1/07378
摘要： A die probe including a probe tip operably connected to a first surface of a thin film; a metal trace, wherein a first portion of the metal trace is operably connected to a second surface of the thin film, the second surface of the thin film opposite the first surface of the thin film; and an upper space transformer, wherein a second portion of the metal trace is operably connected to the upper space transformer, wherein a pressurized liquid and/or gas is configured to expand a space between the second surface of the thin film and the upper space transformer.

3. 发明授权

US11079406B2 Semiconductor micro probe array having compliance 有权
公开(公告)号：US11079406B2
公开(公告)日：2021-08-03
申请号：US15252301
申请日：2016-08-31
申请人： International Business Machines Corporation
发明人： Eugene R. Atwood
IPC分类号： G01R1/067 , G01R1/073 , G01R31/28
摘要： A die probe including a probe tip operably connected to a first surface of a thin film; a metal trace, wherein a first portion of the metal trace is operably connected to a second surface of the thin film, the second surface of the thin film opposite the first surface of the thin film; and an upper space transformer, wherein a second portion of the metal trace is operably connected to the upper space transformer, wherein a pressurized liquid and/or gas is configured to expand a space between the second surface of the thin film and the upper space transformer.

4. 发明授权

US09588177B1 Optimizing generation of test configurations for built-in self-testing 有权
标题翻译：优化内置自检测试配置的生成
公开(公告)号：US09588177B1
公开(公告)日：2017-03-07
申请号：US14987849
申请日：2016-01-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eugene R. Atwood , Mary P. Kusko , Paul J. Logsdon , Franco Motika , Andrew A. Turner
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/317
CPC分类号： G01R31/31707 , G01R31/3187
摘要： Technical solutions are described for optimizing a set of test configurations used for testing an electronic circuit that includes latches. An example method includes receiving a test configuration that includes settings that initiate a set of predetermined input values and corresponding expected output values. The method also includes evaluating the test configuration by executing the electronic circuit according to the test configuration and recording parametric data during the execution, where the parametric data is representative of switching activity of the latches in the electronic circuit. The evaluation includes analyzing the parametric data to identify presence of a predetermined pattern in the switching activity and selecting the test configuration based on the predetermined pattern being absent/present in the switching activity.
摘要翻译：描述了用于优化用于测试包括锁存器的电子电路的一组测试配置的技术解决方案。示例性方法包括接收包括启动一组预定输入值和相应的预期输出值的设置的测试配置。该方法还包括通过根据测试配置执行电子电路并在执行期间记录参数数据来评估测试配置，其中参数数据表示电子电路中的锁存器的切换活动。评估包括分析参数数据以识别切换活动中预定模式的存在，并且基于切换活动中缺少/存在的预定模式来选择测试配置。

5. 发明授权

US09041572B1 Testing a digital-to-analog converter 有权
标题翻译：测试数模转换器
公开(公告)号：US09041572B1
公开(公告)日：2015-05-26
申请号：US14089790
申请日：2013-11-26
申请人： International Business Machines Corporation
发明人： Eugene R. Atwood , Matthew B. Baecher , William R. Kelly , Joseph F. Logan , Pinping Sun
IPC分类号： H03M1/10 , H03M1/66
CPC分类号： H03M1/109 , H03M1/66
摘要： Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.
摘要翻译：测试数字 - 模拟转换器（DAC），其中针对多个数字测试信号值迭代地进行测试，包括：将数字测试信号提供给被测试的DAC和伺服; 由DAC测试的夏天提供模拟测试信号，包括将数字测试信号转换为模拟测试信号; 在夏天向观察锁存器提供包括将模拟测试信号和模拟偏移信号相加的求和信号，从第二DAC接收的模拟偏移信号; 通过观察锁定器向伺服机构提供求和信号的采样; 根据所述采样和所述数字测试信号，通过所述伺服器向所述第二DAC提供数字偏移信号，其中所述第二DAC将所述数字偏移信号转换为所述模拟偏移信号; 并且作为数字观察存储数字偏移信号。

6. 发明授权

US09014254B2 Testing a decision feedback equalizer (‘DFE’) 有权
公开(公告)号：US09014254B2
公开(公告)日：2015-04-21
申请号：US13921470
申请日：2013-06-19
申请人： International Business Machines Corporation
发明人： Eugene R. Atwood , Matthew B. Baecher , Minhan Chen , Hayden C. Cranford, Jr. , William R. Kelly , Todd M. Rasmus
IPC分类号： H03K5/159 , H04B17/00
CPC分类号： H04L1/244 , H04B17/00 , H04B17/20 , H04L25/03057 , H04L25/03248
摘要： Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

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