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1. 发明申请

US20170171005A1 HIGH DATA RATE MULTILEVEL CLOCK RECOVERY SYSTEM 有权
公开(公告)号：US20170171005A1
公开(公告)日：2017-06-15
申请号：US15376348
申请日：2016-12-12
申请人： International Business Machines Corporation
发明人： Matthew B. Baecher , Troy J. Beukema , Lamiaa Msalka
IPC分类号： H04L27/227 , H04L12/26 , H04L25/03
CPC分类号： H04L25/03057 , H04L7/0334 , H04L25/03273 , H04L25/03885 , H04L25/4917 , H04L27/02 , H04L27/2275 , H04L43/028 , H04Q9/06 , H04Q2213/03
摘要： Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

2. 发明申请

US20150198647A1 ON-CHIP TEST FOR INTEGRATED AC COUPLING CAPACITORS 有权
标题翻译：集成式交流耦合电容器的片上测试
公开(公告)号：US20150198647A1
公开(公告)日：2015-07-16
申请号：US14156487
申请日：2014-01-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eugene Atwood , Matthew B. Baecher , John F. Bulzacchelli , Stanislav Polonsky
IPC分类号： G01R31/01 , G01R31/28 , G01R1/30
CPC分类号： G01R31/2884 , G01R31/028
摘要： Apparatus, method and computer program product for determining presence and relative magnitudes of on-chip AC coupling capacitors in a high-speed differential receiver device. A BIST method is employed to ultimately produce a dock count proportional to the fall time of a capacitor, and in the case of differential capacitors a difference in count values. Each capacitor path has a controllable first DAC current or voltage source. A second DAC current or voltage source, later in the data path and isolated from the capacitor node(s), is controlled to offset the voltage contribution of the charged and discharging capacitor. A count is recorded, starting when a capacitor charging current is shut off, and ends (the count) when the voltage of the charged capacitor falls below a threshold. A difference in count between the two data path capacitors is calculated and reported. A state machine operates the sequencing and control of the BIST.
摘要翻译：用于确定高速差分接收机设备中片上AC耦合电容器的存在和相对幅度的装置，方法和计算机程序产品。采用BIST方法来最终产生与电容器的下降时间成比例的对接计数，并且在差分电容器的情况下计数值的差异。每个电容器路径具有可控的第一DAC电流或电压源。控制数据路径中稍后与电容器节点隔离的第二DAC电流或电压源，以抵消充放电电容器的电压贡献。记录计数，从电容器充电电流切断时开始，当充电电容器的电压下降到阈值以下时结束（计数）。计算并报告两个数据通路电容器之间的计数差异。状态机操作BIST的排序和控制。

3. 发明授权

US09762423B2 High data rate multilevel clock recovery system 有权
公开(公告)号：US09762423B2
公开(公告)日：2017-09-12
申请号：US15376361
申请日：2016-12-12
申请人： International Business Machines Corporation
发明人： Matthew B. Baecher , Troy J. Beukema , Lamiaa Msalka
IPC分类号： H04L27/227 , H04L25/03 , H04L12/26 , H04Q9/06
CPC分类号： H04L25/03057 , H04L7/0334 , H04L25/03273 , H04L25/03885 , H04L25/4917 , H04L27/02 , H04L27/2275 , H04L43/028 , H04Q9/06 , H04Q2213/03
摘要： Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

4. 发明授权

US09755863B2 High data rate multilevel clock recovery system 有权
公开(公告)号：US09755863B2
公开(公告)日：2017-09-05
申请号：US15350146
申请日：2016-11-14
申请人： International Business Machines Corporation
发明人： Matthew B. Baecher , Troy J. Beukema , Lamiaa Msalka
IPC分类号： H04L25/03 , H04L27/02
CPC分类号： H04L25/03057 , H04L7/0334 , H04L25/03273 , H04L25/03885 , H04L25/4917 , H04L27/02 , H04L27/2275 , H04L43/028 , H04Q9/06 , H04Q2213/03
摘要： Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

5. 发明授权

US09369263B1 Calibration of sampling phase and aperature errors in multi-phase sampling systems 有权
标题翻译：多相采样系统中采样相位和温度误差的校准
公开(公告)号：US09369263B1
公开(公告)日：2016-06-14
申请号：US14788192
申请日：2015-06-30
申请人： International Business Machines Corporation
发明人： Matthew B. Baecher , John F. Bulzacchelli , John F. Ewen , Gautam Gangasani , Mounir Meghelli, I , Matthew J. Paschal , Trushil N. Shah
IPC分类号： H04L7/00 , H04L7/06 , H04B17/21
CPC分类号： H04B17/21 , G01R25/00 , H03K5/1565 , H04L1/24
摘要： Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal. The method adjusts a first phase sampling clock signal output of an electronic phase rotator device to provide an initial alignment setting against a first edge of the reference output signal; and then implements phase calibration logic to align a second phase sampling clock signal against a second edge.
摘要翻译：校准多相采样系统采样相位的方法和装置。该方法包括片上生成用于从数据路径生成至少一个参考输出信号的原始相位参考图形信号; 响应于时钟信号采样所述至少一个参考输出信号以获得采样; 以及修改所述时钟信号的相位以将所获得的样本对准至少一个参考输出信号的图形边缘。从输入到数据通道的原始相位参考图形信号中去除对称和非对称占空比失真。通过周期性地反转至少一个参考输出信号来消除相位校准时数据通路输出信号中的非对称失真的影响。该方法调节电子相位旋转器装置的第一相位采样时钟信号输出以针对参考输出信号的第一边沿提供初始对准设置; 然后实施相位校准逻辑以将第二相位采样时钟信号与第二边沿对准。

6. 发明授权

US09735988B2 High data rate multilevel clock recovery system 有权
公开(公告)号：US09735988B2
公开(公告)日：2017-08-15
申请号：US15376319
申请日：2016-12-12
申请人： International Business Machines Corporation
发明人： Matthew B. Baecher , Troy J. Beukema , Lamiaa Msalka
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L7/0334 , H04L25/03273 , H04L25/03885 , H04L25/4917 , H04L27/02 , H04L27/2275 , H04L43/028 , H04Q9/06 , H04Q2213/03
摘要： Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

7. 发明授权

US09712347B2 High data rate multilevel clock recovery system 有权
公开(公告)号：US09712347B2
公开(公告)日：2017-07-18
申请号：US15376337
申请日：2016-12-12
申请人： International Business Machines Corporation
发明人： Matthew B. Baecher , Troy J. Beukema , Lamiaa Msalka
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L7/0334 , H04L25/03273 , H04L25/03885 , H04L25/4917 , H04L27/02 , H04L27/2275 , H04L43/028 , H04Q9/06 , H04Q2213/03
摘要： Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

8. 发明授权

US09705717B2 High data rate multilevel clock recovery system 有权
公开(公告)号：US09705717B2
公开(公告)日：2017-07-11
申请号：US15376348
申请日：2016-12-12
申请人： International Business Machines Corporation
发明人： Matthew B. Baecher , Troy J. Beukema , Lamiaa Msalka
IPC分类号： H04L27/227 , H04L25/03 , H04L12/26
CPC分类号： H04L25/03057 , H04L7/0334 , H04L25/03273 , H04L25/03885 , H04L25/4917 , H04L27/02 , H04L27/2275 , H04L43/028 , H04Q9/06 , H04Q2213/03
摘要： Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

9. 发明申请

US20170170994A1 HIGH DATA RATE MULTILEVEL CLOCK RECOVERY SYSTEM 有权
公开(公告)号：US20170170994A1
公开(公告)日：2017-06-15
申请号：US15350146
申请日：2016-11-14
申请人： International Business Machines Corporation
发明人： Matthew B. Baecher , Troy J. Beukema , Lamiaa Msalka
IPC分类号： H04L25/03 , H04L27/02
CPC分类号： H04L25/03057 , H04L7/0334 , H04L25/03273 , H04L25/03885 , H04L25/4917 , H04L27/02 , H04L27/2275 , H04L43/028 , H04Q9/06 , H04Q2213/03
摘要： Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

10. 发明授权

US09041572B1 Testing a digital-to-analog converter 有权
标题翻译：测试数模转换器
公开(公告)号：US09041572B1
公开(公告)日：2015-05-26
申请号：US14089790
申请日：2013-11-26
申请人： International Business Machines Corporation
发明人： Eugene R. Atwood , Matthew B. Baecher , William R. Kelly , Joseph F. Logan , Pinping Sun
IPC分类号： H03M1/10 , H03M1/66
CPC分类号： H03M1/109 , H03M1/66
摘要： Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.
摘要翻译：测试数字 - 模拟转换器（DAC），其中针对多个数字测试信号值迭代地进行测试，包括：将数字测试信号提供给被测试的DAC和伺服; 由DAC测试的夏天提供模拟测试信号，包括将数字测试信号转换为模拟测试信号; 在夏天向观察锁存器提供包括将模拟测试信号和模拟偏移信号相加的求和信号，从第二DAC接收的模拟偏移信号; 通过观察锁定器向伺服机构提供求和信号的采样; 根据所述采样和所述数字测试信号，通过所述伺服器向所述第二DAC提供数字偏移信号，其中所述第二DAC将所述数字偏移信号转换为所述模拟偏移信号; 并且作为数字观察存储数字偏移信号。

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