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1. 发明授权

US09041572B1 Testing a digital-to-analog converter 有权
标题翻译：测试数模转换器
公开(公告)号：US09041572B1
公开(公告)日：2015-05-26
申请号：US14089790
申请日：2013-11-26
申请人： International Business Machines Corporation
发明人： Eugene R. Atwood , Matthew B. Baecher , William R. Kelly , Joseph F. Logan , Pinping Sun
IPC分类号： H03M1/10 , H03M1/66
CPC分类号： H03M1/109 , H03M1/66
摘要： Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.
摘要翻译：测试数字 - 模拟转换器（DAC），其中针对多个数字测试信号值迭代地进行测试，包括：将数字测试信号提供给被测试的DAC和伺服; 由DAC测试的夏天提供模拟测试信号，包括将数字测试信号转换为模拟测试信号; 在夏天向观察锁存器提供包括将模拟测试信号和模拟偏移信号相加的求和信号，从第二DAC接收的模拟偏移信号; 通过观察锁定器向伺服机构提供求和信号的采样; 根据所述采样和所述数字测试信号，通过所述伺服器向所述第二DAC提供数字偏移信号，其中所述第二DAC将所述数字偏移信号转换为所述模拟偏移信号; 并且作为数字观察存储数字偏移信号。

2. 发明授权

US09014254B2 Testing a decision feedback equalizer (‘DFE’) 有权
公开(公告)号：US09014254B2
公开(公告)日：2015-04-21
申请号：US13921470
申请日：2013-06-19
申请人： International Business Machines Corporation
发明人： Eugene R. Atwood , Matthew B. Baecher , Minhan Chen , Hayden C. Cranford, Jr. , William R. Kelly , Todd M. Rasmus
IPC分类号： H03K5/159 , H04B17/00
CPC分类号： H04L1/244 , H04B17/00 , H04B17/20 , H04L25/03057 , H04L25/03248
摘要： Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

3. 发明授权

US09209948B2 Testing a decision feedback equalizer (‘DFE’) 有权
标题翻译：测试反馈均衡器（'DFE'）
公开(公告)号：US09209948B2
公开(公告)日：2015-12-08
申请号：US14599605
申请日：2015-01-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eugene R. Atwood , Matthew B. Baecher , Minhan Chen , Hayden C. Cranford, Jr. , William R. Kelly , Todd M. Rasmus
IPC分类号： H04B17/00 , H04L1/24 , H04L25/03 , H04B17/20
CPC分类号： H04L1/244 , H04B17/00 , H04B17/20 , H04L25/03057 , H04L25/03248
摘要： Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
摘要翻译：测试判决反馈均衡器（DFE），DFE包括可操作地耦合到多个锁存器的加法放大器和用于接收数据信号的输入信号线，包括：防止差分数据信号被加法放大器接收; 并对每个要测试的水龙头进行迭代：将每个水龙头的抽头系数设置为零; 将所述多个锁存器的输出设置为预定值; 将要测试的水龙头的抽头系数设置为满量程值; 以及确定来自所述DFE的合成输出信号是否与预定的预期输出信号匹配。

4. 发明申请

US20140149629A1 SYSTEMS AND METHODS FOR SIGNAL DETECTION 有权
标题翻译：用于信号检测的系统和方法
公开(公告)号：US20140149629A1
公开(公告)日：2014-05-29
申请号：US13781669
申请日：2013-02-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Hayden C. Cranford, JR. , Daniel M. Dreps , William R. Kelly
IPC分类号： G06F13/38
CPC分类号： G06F13/423 , G06F2213/0026 , Y02D10/14 , Y02D10/151
摘要： Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct.
摘要翻译：用于在PCI Express接口检测一个或多个信号的方法包括由PCI Express接口的接收器接收信号。所述方法还包括识别一个或多个数据采样点以设置振幅阈值。此外，该方法包括将接收信号的幅度与振幅阈值进行比较。该方法还包括当信号的幅度在预定时间段内大于或等于振幅阈值中的至少一个时，确认接收信号是有效信号。该方法还包括禁用PCI Express接口的信号检测器以节省电力。信号检测器被配置为检测一个或多个低频信号; 并检测检测到的信号是否正确。

5. 发明申请

US20140149627A1 SYSTEMS AND METHODS FOR SIGNAL DETECTION 有权
标题翻译：用于信号检测的系统和方法
公开(公告)号：US20140149627A1
公开(公告)日：2014-05-29
申请号：US13685583
申请日：2012-11-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Hayden C. Cranford, JR. , Daniel M. Dreps , William R. Kelly
IPC分类号： G06F13/38
CPC分类号： G06F13/423 , G06F2213/0026 , Y02D10/14 , Y02D10/151
摘要： A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct.
摘要翻译：用于在PCI Express接口处检测一个或多个信号的系统包括被配置为在PCI Express接口处接收信号的接收机，以及被配置为基于电平感测来检测一个或多个信号的峰值检测器，并且识别一个或多个数据采样点设置振幅阈值。比较器被配置为将接收信号的幅度与幅度阈值进行比较，并且处理器被配置为当信号的幅度是大于或等于幅度的至少一个时，确认接收信号是有效信号阈值超过预定义的时间段。处理器还被配置为禁用可以检测一个或多个低频信号的信号检测器。该系统还包括测试器，其被配置为测试检测到的信号是否正确。

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