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1. 发明授权

US09184948B2 Decision feedback equalizer (‘DFE’) with a plurality of independently-controlled isolated power domains 有权
标题翻译：具有多个独立控制的隔离电源域的判决反馈均衡器（“DFE”）
公开(公告)号：US09184948B2
公开(公告)日：2015-11-10
申请号：US13903199
申请日：2013-05-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Minhan Chen , Steven M. Clements , Carrie E. Cox , Todd M. Rasmus
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/03
CPC分类号： H04L25/03146
摘要： A Decision Feedback Equalizer (‘DFE’) that includes: a plurality of input signal lines comprising at least one data signal line and a plurality of power control signal lines; at least one output signal line; and a plurality of independently-controlled isolated power domains, where each independently-controlled isolated power domain is coupled to a corresponding one of the power control signal lines, each of the power control signal lines configured to transmit a power control signal to the independently-controlled isolated power domain dynamically, and each independently-controlled isolated power domain selectively consumes power in response to the power control signal, each independently-controlled isolated power domain configured to be dynamically powered up or powered down without impacting signal processing operations.
摘要翻译：一种判决反馈均衡器（“DFE”），包括：包括至少一个数据信号线和多个功率控制信号线的多个输入信号线; 至少一个输出信号线; 以及多个独立控制的隔离电源域，其中每个独立控制的隔离电源区域耦合到相应的一个功率控制信号线，每个功率控制信号线被配置为将功率控制信号发送到独立控制的隔离电源区域，并且每个独立控制的隔离电力区域响应于功率控制信号而选择性地消耗功率，每个独立控制的隔离电源域被配置为在不影响信号处理操作的情况下动态上电或掉电。

2. 发明授权

US09014254B2 Testing a decision feedback equalizer (‘DFE’) 有权
公开(公告)号：US09014254B2
公开(公告)日：2015-04-21
申请号：US13921470
申请日：2013-06-19
申请人： International Business Machines Corporation
发明人： Eugene R. Atwood , Matthew B. Baecher , Minhan Chen , Hayden C. Cranford, Jr. , William R. Kelly , Todd M. Rasmus
IPC分类号： H03K5/159 , H04B17/00
CPC分类号： H04L1/244 , H04B17/00 , H04B17/20 , H04L25/03057 , H04L25/03248
摘要： Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

3. 发明授权

US09209948B2 Testing a decision feedback equalizer (‘DFE’) 有权
标题翻译：测试反馈均衡器（'DFE'）
公开(公告)号：US09209948B2
公开(公告)日：2015-12-08
申请号：US14599605
申请日：2015-01-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Eugene R. Atwood , Matthew B. Baecher , Minhan Chen , Hayden C. Cranford, Jr. , William R. Kelly , Todd M. Rasmus
IPC分类号： H04B17/00 , H04L1/24 , H04L25/03 , H04B17/20
CPC分类号： H04L1/244 , H04B17/00 , H04B17/20 , H04L25/03057 , H04L25/03248
摘要： Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
摘要翻译：测试判决反馈均衡器（DFE），DFE包括可操作地耦合到多个锁存器的加法放大器和用于接收数据信号的输入信号线，包括：防止差分数据信号被加法放大器接收; 并对每个要测试的水龙头进行迭代：将每个水龙头的抽头系数设置为零; 将所述多个锁存器的输出设置为预定值; 将要测试的水龙头的抽头系数设置为满量程值; 以及确定来自所述DFE的合成输出信号是否与预定的预期输出信号匹配。

4. 发明授权

US08803569B1 Ramp generator using operational amplifier based integration and switched capacitor techniques 有权
标题翻译：使用基于运算放大器的积分和开关电容技术的斜坡发生器
公开(公告)号：US08803569B1
公开(公告)日：2014-08-12
申请号：US13928466
申请日：2013-06-27
申请人： International Business Machines Corporation
发明人： Anjali R. Malladi , Todd M. Rasmus , Pradeep Thiagarajan
IPC分类号： H03K4/06
CPC分类号： H03K4/066
摘要： A ramp generator circuit for generating sawtooth waveforms based on a clock signal may include an operational amplifier, a first switched capacitor device within a first feedback path of the operational amplifier, and a first plurality of switch devices within the first feedback path, whereby upon actuation of the first plurality of switches, the first switched capacitor generates first ramp waveforms during first alternate clock periods of the clock signal. The circuit may also include a second switched capacitor device within a second feedback path of the operational amplifier, and a second plurality of switch devices within the second feedback path, whereby upon actuation of the second plurality of switches, the second switched capacitor generates second ramp waveforms during second alternate clock periods of the clock signal. The first alternate clock periods of the clock are followed by an adjacent one of the second alternate clock periods of the clock.
摘要翻译：用于基于时钟信号产生锯齿波形的斜坡发生器电路可以包括运算放大器，运算放大器的第一反馈路径内的第一开关电容器器件和第一反馈通路内的第一多个开关器件，由此在致动时在第一多个开关中，第一开关电容器在时钟信号的第一替代时钟周期期间产生第一斜坡波形。电路还可以包括运算放大器的第二反馈路径内的第二开关电容器器件和第二反馈通路内的第二多个开关器件，由此在第二多个开关致动时，第二开关电容器产生第二斜坡时钟信号的第二个交替时钟周期内的波形。时钟的第一替代时钟周期之后是时钟的第二替代时钟周期中的相邻的时钟周期。

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