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1. 发明申请

US20070150699A1 Firm partitioning in a system with a point-to-point interconnect 审中-公开
标题翻译：在具有点对点互连的系统中进行牢固的分区
公开(公告)号：US20070150699A1
公开(公告)日：2007-06-28
申请号：US11321213
申请日：2005-12-28
申请人： Ioannis Schoinas , Doddaballapur Jayasimha , Eric Delano , Allen Baum , Akhilesh Kumar , Steven Chang , Suresh Chittor , Kenneth Creta , Stephen Van Doren
发明人： Ioannis Schoinas , Doddaballapur Jayasimha , Eric Delano , Allen Baum , Akhilesh Kumar , Steven Chang , Suresh Chittor , Kenneth Creta , Stephen Van Doren
IPC分类号： G06F15/00
CPC分类号： H04L45/00 , H04L45/04
摘要： Methods and apparatuses for firm partitioning of a computing platform.
摘要翻译：用于计算平台的固定分区的方法和装置。

2. 发明授权

US06976115B2 Peer-to-peer bus segment bridging 有权
标题翻译：点对点公交线路桥接
公开(公告)号：US06976115B2
公开(公告)日：2005-12-13
申请号：US10112344
申请日：2002-03-28
申请人： Kenneth Creta , Jasmin Ajanovic , Joseph Bennett
发明人： Kenneth Creta , Jasmin Ajanovic , Joseph Bennett
IPC分类号： G06F3/00 , G06F13/36 , G06F13/40
CPC分类号： G06F13/4031
摘要： A method and apparatus are described for facilitating proper ordering of peer-to-peer communications between bridged bus segments. According to one embodiment of the present invention a fence command is issued when a peer-to-peer communication between devices on separate bus segments connected on the same side of a bridge is detected. The fence command is inserted into a plurality of buffers in an I/O hub corresponding to the bus segments to force temporary ordering across all pipes of the I/O hub. The hub prohibits processing of subsequent commands from a buffer once a fence command has been read from that buffer until a corresponding fence command is read from all other buffers in the plurality of buffers therby assuring proper ordering of the peer-to-peer communication.
摘要翻译：描述了一种用于促进桥接总线段之间的对等通信的正确排序的方法和装置。根据本发明的一个实施例，当检测到连接在桥的同一侧上的分开的总线段上的设备之间的对等通信时，发出围栏命令。 fence命令插入到与总线段相对应的I / O集线器中的多个缓冲器中，以迫使临时排序I / O集线器的所有管道。一旦从该缓冲器读取了fence命令，则该中继器禁止处理来自缓冲器的后续命令，直到从多个缓冲器中的所有其他缓冲器读取相应的fence命令，从而确保对等通信的正确排序。

3. 发明申请

US20060136611A1 Chipset feature detection and configuration by an I/O device 有权
标题翻译：芯片组特征检测和I / O设备配置
公开(公告)号：US20060136611A1
公开(公告)日：2006-06-22
申请号：US10750060
申请日：2003-12-30
申请人： William Futral , Kenneth Creta , Sujoy Sen , Gregory Cummings , Sivakumar Radhakrishnan
发明人： William Futral , Kenneth Creta , Sujoy Sen , Gregory Cummings , Sivakumar Radhakrishnan
IPC分类号： G06F13/28
CPC分类号： G06F13/4027
摘要： Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.
摘要翻译：用于第一设备的第二设备查询第二设备内的硬件特征的可用性的装置和方法，以及第二设备接收和分析查询以确定是否响应，取决于所寻求的硬件特征的版本，识别供应商等的代码，并且如果确定作出回复，则响应提供硬件特征的可用性的指示和/或可以访问硬件特征的地址。

4. 发明授权

US5742831A Methods and apparatus for maintaining cache coherency during copendency of load and store operations 失效
标题翻译：用于在加载和存储操作的一致性期间维持高速缓存一致性的方法和装置
公开(公告)号：US5742831A
公开(公告)日：1998-04-21
申请号：US268338
申请日：1994-06-30
申请人： Kenneth Creta
发明人： Kenneth Creta
IPC分类号： G06F9/38 , G06F12/08 , G06F13/16
CPC分类号： G06F9/3824 , G06F12/0859 , G06F12/0875
摘要： Methods and apparatus for maintaining cache coherency for pending load operations. A processor is selectively stalling only when there exists certain relationships between the address of an incoming store instruction and the addresses of the pending load instructions. The address specified by an incoming store instruction is compared with all the addresses specified by the pending load instructions that are stored in a bus queue. The processor is stalled from issuing subsequent instructions and executing the store instruction if the comparison results in a match of the store instruction address with any of the addresses of the pending load instructions. Instruction issue and execution of the store instruction are unstalled when data from the matching load instruction address returns. Alternatively, a count of the number of load instructions pending in the bus queue for each specified address may be maintained. Upon receiving a store instruction, a stall occurs if the count for a corresponding address specified by the store instruction is non-zero. The count for an address specified by a load instruction is incremented if the load instruction misses the cache. When the requested data returns from external memory, the count for the address specified by the missed load instruction is decremented. When data from the load instruction address that matches the store instruction address returns and the count for the address specified by the stalled store instruction is zero, then instruction issue and execution of the store instruction are unstalled.
摘要翻译：用于维持缓存一致性的待处理加载操作的方法和设备。只有当存在进入存储指令的地址与待处理加载指令的地址之间存在一定关系时，处理器才选择性地停止。由输入存储指令指定的地址与存储在总线队列中的待处理加载指令指定的所有地址进行比较。如果比较导致存储指令地址与待处理加载指令的任何地址的匹配，则处理器停止发出后续指令并执行存储指令。来自匹配加载指令地址的数据返回时，存储指令的指令发出和执行被解除。或者，可以维护针对每个指定地址的总线队列中待处理的加载指令的数量的计数。收到存储指令后，如果存储指令指定的相应地址的计数为非零，则会发生停止。如果加载指令丢失缓存，则由加载指令指定的地址的计数将递增。当请求的数据从外部存储器返回时，由缺省加载指令指定的地址的计数递减。当来自与存储指令地址匹配的加载指令地址的数据返回，并且由停止的存储指令指定的地址的计数为零时，指令发出和存储指令的执行被解除。

5. 发明申请

US20050251612A1 Separating transactions into different virtual channels 有权
标题翻译：将事务分为不同的虚拟通道
公开(公告)号：US20050251612A1
公开(公告)日：2005-11-10
申请号：US10833236
申请日：2004-04-27
申请人： Kenneth Creta , Aaron Spink , Robert Blankenship
发明人： Kenneth Creta , Aaron Spink , Robert Blankenship
IPC分类号： H04L29/00 , G06F13/12 , G06F13/36 , G06F13/376 , G06F15/16
CPC分类号： G06F13/36 , G06F13/12
摘要： In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third channel, based upon a type of the incoming transactions. The incoming transactions may be sent by a peer device coupled to the coherent system. By separating the transactions based on type, deadlocks may be avoided.
摘要翻译：在本发明的一个实施例中，一种方法可以包括基于传入事务的类型，将输入事务分离为至少第一信道，第二信道和第三信道的至少第一信道，相干系统的代理。传入的事务可以由耦合到相干系统的对等设备发送。通过基于类型分离事务，可能会避免死锁。

6. 发明申请

US20050251611A1 Transmitting peer-to-peer transactions through a coherent interface 有权
标题翻译：通过一致的界面传输对等交易
公开(公告)号：US20050251611A1
公开(公告)日：2005-11-10
申请号：US10832607
申请日：2004-04-27
申请人： Kenneth Creta , Robert Blankenship , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth Creta , Robert Blankenship , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F13/36 , G06F13/38 , G06F13/42
CPC分类号： G06F13/387 , G06F13/4265
摘要： In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device using the second header information. In one such embodiment, the first header may be a header of a first protocol and the second header may be of a different protocol that is used to tunnel the transaction through the coherent system.
摘要翻译：在各种实施例中，本发明包括一种用于在相干系统的第一代理处从第一对等设备接收具有第一报头信息的交易的方法，将第二报头信息插入事务，并且使用第二标题信息。在一个这样的实施例中，第一报头可以是第一协议的报头，并且第二报头可以是用于通过相干系统隧道交易的不同协议。

7. 发明申请

US20050235067A1 Write combining protocol between processors and chipsets 失效
标题翻译：在处理器和芯片组之间写入组合协议
公开(公告)号：US20050235067A1
公开(公告)日：2005-10-20
申请号：US10828872
申请日：2004-04-20
申请人： Kenneth Creta , Aaron Spink , Lance Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
发明人： Kenneth Creta , Aaron Spink , Lance Hacking , Sridhar Muthrasanallur , Jasmin Ajanovic
IPC分类号： G06F13/14 , G06F13/40
CPC分类号： G06F13/4027
摘要： Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
摘要翻译：处理写事务的系统和方法提供了根据I / O集线器和处理器之间的协议在输入/输出（I / O）集线器上组合写事务。与写入事务相关的数据可以刷新到I / O设备，而不需要I / O设备内的专有软件和专用寄存器。

8. 发明申请

US20050210229A1 Method and system for configuration of processor integrated devices in multi-processor systems 审中-公开
标题翻译：在多处理器系统中配置处理器集成设备的方法和系统
公开(公告)号：US20050210229A1
公开(公告)日：2005-09-22
申请号：US10806787
申请日：2004-03-22
申请人： Prashant Sethi , Kenneth Creta , Raymond Tetrick
发明人： Prashant Sethi , Kenneth Creta , Raymond Tetrick
IPC分类号： G06F15/16 , G06F9/445 , G06F13/40 , G06F9/00
CPC分类号： G06F13/4027
摘要： The ability to configure an integrated device with a decoder in a processor or network component according to PCI or PCI Express interconnects.
摘要翻译：根据PCI或PCI Express互连，能够在处理器或网络组件中配置具有解码器的集成设备。

9. 发明申请

US20060136639A1 Stream priority 有权
公开(公告)号：US20060136639A1
公开(公告)日：2006-06-22
申请号：US11020500
申请日：2004-12-21
申请人： William Futral , Kenneth Creta , Sujoy Sen , Gregory Cummings , Sivakumar Radhakrishnan
发明人： William Futral , Kenneth Creta , Sujoy Sen , Gregory Cummings , Sivakumar Radhakrishnan
IPC分类号： G06F13/14
CPC分类号： G06F13/4291
摘要： A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.

10. 发明申请

US20060101183A1 Technique for broadcasting messages on a point-to-point interconnect 有权
公开(公告)号：US20060101183A1
公开(公告)日：2006-05-11
申请号：US10984527
申请日：2004-11-08
申请人： Keshavan Tiruvallur , Kenneth Creta , Robert Blankenship
发明人： Keshavan Tiruvallur , Kenneth Creta , Robert Blankenship
IPC分类号： G06F13/14
CPC分类号： G06F13/36
摘要： A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect.

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