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1. 发明申请

US20120170088A1 MEMS Spatial Light Modulator Driver Calibration Systems 审中-公开
标题翻译： MEMS空间光调制器驱动器校准系统
公开(公告)号：US20120170088A1
公开(公告)日：2012-07-05
申请号：US12983197
申请日：2010-12-31
申请人： Ion E. Opris , Vlad Novotny , Paul Richard Routley
发明人： Ion E. Opris , Vlad Novotny , Paul Richard Routley
IPC分类号： G02B26/00 , G03H1/08
CPC分类号： G02B26/0841 , G03H1/2294 , G03H2001/0224 , G03H2225/24 , G03H2225/32
摘要： We describe a method of compensating for long-term mechanical property changes in an analogue optical MEMS SLM. In embodiments the SLM comprises multiple piston-type actuation optical phase modulating pixels each having a mirror with a variable height determined by an analogue voltage applied to a corresponding pixel electrode. The method comprises performing initial calibrations of the analogue displacement and pixel capacitance versus analogue voltage to determine a relationship between the pixel capacitance and analogue displacement, and then updating the displacement-voltage capacitance using the initial calibration data and a later calibration of the analogue voltage-capacitance characteristic of a pixel.
摘要翻译：我们描述了在模拟光学MEMS SLM中补偿长期机械性能变化的方法。在实施例中，SLM包括多个活塞式致动光学相位调制像素，每个具有由施加到相应像素电极的模拟电压确定的可变高度的反射镜。该方法包括执行模拟位移和像素电容对模拟电压的初始校准，以确定像素电容和模拟位移之间的关系，然后使用初始校准数据和模拟电压 - 电压的稍后校准来更新位移电压电容，像素的电容特性。

2. 发明授权

US06426669B1 Low voltage bandgap reference circuit 有权
标题翻译：低电压带隙基准电路
公开(公告)号：US06426669B1
公开(公告)日：2002-07-30
申请号：US09640897
申请日：2000-08-18
申请人： Jay Friedman , Ion E. Opris
发明人： Jay Friedman , Ion E. Opris
IPC分类号： G05F1100
CPC分类号： G05F3/30
摘要： In a bandgap voltage reference circuit in accordance with the present invention, the different-sized emitters of the two bipolar devices of a &Dgr;VBE stage return to ground (or other bias voltage) through separate resistors. The VBE term of the reference device is supplied by a VBE current source through a third resistor. The proportional-to-absolute-temperature (PTAT) term of the reference occurs as the difference of base-emitter voltages &Dgr;VBE between the larger and smaller emitters. An output voltage Vout multiplier resistor feeds to the larger emitter through an inverting amplifier. In one embodiment of the invention, the output voltage Vout trim at one temperature is obtained by trimming the base-emitter resistor of the “small emitter” device to compensate for the VBE process variation.
摘要翻译：在根据本发明的带隙电压参考电路中，DELTAVBE级的两个双极性器件的不同大小的发射极通过单独的电阻返回到地（或其他偏置电压）。参考装置的VBE项由VBE电流源通过第三电阻提供。参考的比例绝对温度（PTAT）项出现在较大和较小发射极之间的基极 - 发射极电压差ΔTATABE之间。输出电压Vout乘法器电阻通过反相放大器馈送到较大的发射极。在本发明的一个实施例中，通过微调“小发射极”器件的基极 - 发射极电阻来补偿VBE过程变化，从而获得在一个温度下的输出电压Vout微调。

3. 发明授权

US06407622B1 Low-voltage bandgap reference circuit 失效
标题翻译：低压带隙基准电路
公开(公告)号：US06407622B1
公开(公告)日：2002-06-18
申请号：US09804779
申请日：2001-03-13
申请人： Ion E. Opris
发明人： Ion E. Opris
IPC分类号： G05F110
CPC分类号： G05F3/30
摘要： A low-voltage reference circuit is provided wherein (i) the output voltage can be set to be a fraction of the silicon bandgap voltage of 1.206 volts, or on the order of 0.9 volts, (ii) the output voltage can have a zero thermal coefficient (TC), and (iii) the operating supply voltage Vcc can be less than 1.5 volts, or on the order of 1.1 volts. In one embodiment, the reference circuit modifies a conventional Brokaw bandgap circuit to lower both the required Vcc level and the output voltage by a constant offset. Referring to FIG. 3, the modification includes adding bipolar transistor (Q6), an opamp (A3) and resistors (R5, R6 and R7). In another embodiment, the reference circuit modifies a conventional circuit with PNP transistors connected to the substrate, referring to FIG. 4, by adding current source I6, NMOS transistor M3, opamp A4 and resistors R8-R10. A further embodiment modifies FIG. 4, referring to FIG. 5, by omitting the current source I6, and moving the location of resistor R4.
摘要翻译：提供了一种低电压参考电路，其中（i）输出电压可以被设置为1.206伏特的硅带隙电压的一部分，或大约为0.9伏，（ii）输出电压可以具有零热系数（TC），和（iii）工作电源电压Vcc可以小于1.5伏，或者大约1.1伏。在一个实施例中，参考电路修改常规的Brokaw带隙电路，以将所需的Vcc电平和输出电压降低一个恒定的偏移。参考图如图3所示，修改包括添加双极晶体管（Q6），运算放大器（A3）和电阻器（R5，R6和R7）。在另一个实施例中，参考电路通过连接到衬底的PNP晶体来修改常规电路。如图4所示，通过添加电流源I6，NMOS晶体管M3，运算放大器A4和电阻器R8-R10。另一实施例修改图。参照图4。如图5所示，省略电流源I6，并移动电阻R4的位置。

4. 发明授权

US06166779A Method for analog decimation of image signals 有权
标题翻译：图像信号的模拟抽取方法
公开(公告)号：US06166779A
公开(公告)日：2000-12-26
申请号：US300816
申请日：1999-04-27
申请人： Shingo Kokudo , Jonathan A. Kleks , Ion E. Opris
发明人： Shingo Kokudo , Jonathan A. Kleks , Ion E. Opris
IPC分类号： H04N5/14 , G11C27/02 , H03M1/12 , H04B14/04 , H04N5/225 , H04N5/52 , H04N5/335
CPC分类号： H04N5/23241 , G11C27/024 , H03M1/1245
摘要： In a digital image processing device such as a portable digital camera, an analog decimation circuit is provided as a front end for the digital video imaging circuit so that the data rate is reduced without substantial loss in fidelity so that the power dissipation is minimized. In a decimation circuit, the data rate is reduced by reducing only higher frequency spectral components of a captured image without substantial loss in fidelity of the remaining spectral components of the captured image. The required amount of digital data processing is so substantially reduced that considerable power savings result. A mixture of decimation modes may be effected using the same circuit.
摘要翻译：在诸如便携式数字照相机的数字图像处理装置中，提供模拟抽取电路作为数字视频成像电路的前端，从而降低数据速率，而不会在保真度方面实质上损耗，从而使功耗最小化。在抽取电路中，通过仅捕获拍摄图像的较高频谱分量的降低而降低数据速率，而不会在拍摄图像的剩余频谱分量的保真度方面实质上损失。所需的数字数据处理量大大降低，从而导致显着的功率节省。可以使用相同的电路来实现抽取模式的混合。

5. 发明授权

US6097326A Algorithmic analog-to-digital converter with reduced differential non-linearity and method 失效
标题翻译：具有降低差分非线性和方法的算法模数转换器
公开(公告)号：US6097326A
公开(公告)日：2000-08-01
申请号：US84543
申请日：1998-05-26
申请人： Ion E. Opris , Sing W. Chin , Bill C. Wong , Satoshi Sakurai
发明人： Ion E. Opris , Sing W. Chin , Bill C. Wong , Satoshi Sakurai
IPC分类号： H03M1/06 , H03M1/44 , H03M1/38
CPC分类号： H03M1/442 , H03M1/0612
摘要： An analog to digital converter section for use in an analog to digital converter which includes a converter stage which produces a digital and an residue output. The residue output is applied to an over-range stage which produces a second residue output equal to the first residue output reduced in magnitude by the magnitude of a reference voltage. The over-range stage is capable of operating with a relatively high feedback factor to increase operating speed and with commutated feedback-capacitor switching to reduce differential non-linearity errors.
摘要翻译：一种用于模数转换器的模数转换器部分，其包括产生数字和残留输出的转换器级。剩余输出被施加到超范围级，其产生等于第一残余输出的第二残余输出，其大小减小参考电压的幅度。超范围级能够以相对较高的反馈因子运行，以提高运行速度，并具有换向反馈电容器切换以减少差分非线性误差。

6. 发明授权

US6060912A High speed strobed comparator circuit having a latch circuit 失效
标题翻译：具有锁存电路的高速选通比较器电路
公开(公告)号：US6060912A
公开(公告)日：2000-05-09
申请号：US933781
申请日：1997-09-19
申请人： Ion E. Opris , Laurence D. Lewicki
发明人： Ion E. Opris , Laurence D. Lewicki
IPC分类号： H03K3/356 , G11C7/06
CPC分类号： H03K3/35613 , H03M1/0872 , H03M1/38
摘要： A strobed comparator circuit with reduced signal propagation time has a regenerative latch in which, during the reset phase of operation, its output nodes are discharged to a common potential which is close to the regenerative voltage level of the cross-coupled transistors forming such regenerative latch rather than to circuit ground. Accordingly, overall signal propagation time is reduced by the amount of reduction in charging time necessary for one of the discharged nodes to recharge above the threshold voltage of one of the cross-coupled latch transistors. Also included is an output monitoring circuit which determines whether the regenerative latch has remained in a metastable state.
摘要翻译：具有减小的信号传播时间的选通比较器电路具有再生锁存器，其中在复位操作阶段期间，其输出节点被放电到接近形成这种再生锁存器的交叉耦合晶体管的再生电压电平的公共电位而不是电路接地。因此，整个信号传播时间减少了放电节点之一所需的充电时间的减少量超过交叉耦合的锁存晶体管中的一个的阈值电压。还包括输出监视电路，其确定再生锁存器是否保持在亚稳态。

7. 发明授权

US09417272B1 Binary coded, arbitrarily shaped received signal strength indicator 有权
标题翻译：二进制编码，任意形状的接收信号强度指示
公开(公告)号：US09417272B1
公开(公告)日：2016-08-16
申请号：US14102648
申请日：2013-12-11
申请人： Ion E. Opris
发明人： Ion E. Opris
IPC分类号： H03M1/34 , G01R21/00 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5063 , H04B17/318
摘要： A received signal strength indicator (RSSI) receives an input voltage. The input voltage is amplified by a cascade of voltage amplifiers. The output of each amplifier is squared by a squarer. The output of each squarer is then compared to an array of fixed values from a strictly monotonic sequence. The comparators outputs are fed to a digital thermometer decoder, the outputs of which represent the binary coded, arbitrarily shaped RSSI. The squarer can be implemented using two MOS transistors, and has a current output. The comparators can be implemented using multiple current mirrors.
摘要翻译：接收到的信号强度指示器（RSSI）接收输入电压。输入电压由级联的电压放大器放大。每个放大器的输出平方为平方。然后将每个平方的输出与来自严格单调序列的固定值的数组进行比较。比较器输出被馈送到数字温度计解码器，其输出表示二进制编码的任意形状的RSSI。平方器可以使用两个MOS晶体管实现，并具有电流输出。比较器可以使用多个电流镜来实现。

8. 发明授权

US08928409B1 Trans-capacitance amplifier with picoAmperes input biasing and large output swing 有权
标题翻译：具有picoAmperes输入偏置和大输出摆幅的跨电容放大器
公开(公告)号：US08928409B1
公开(公告)日：2015-01-06
申请号：US13940261
申请日：2013-07-12
申请人： Ion E. Opris
发明人： Ion E. Opris
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45475 , H03F3/45946 , H03F2200/153 , H03F2203/45114 , H03F2203/45294 , H03F2203/45408 , H03F2203/45512 , H03F2203/45521 , H03F2203/45674
摘要： According to some embodiments, a trans-capacitance amplifier is exhibiting an input current of the biasing in the range of picoAmperes while allowing large output swings. The trans-capacitance amplifier comprises an operational amplifier, a feedback capacitor, circuitry to DC bias and to AC ground the non-inverting input of the operational amplifier, and circuitry to DC bias the inverting input of the operational amplifier. According to some embodiments, the circuitry to bias the inverting input comprises a cascade of degenerated differential pairs. The first transistor of the first pair and the second transistor of the last pair have an active load. The cascade of differential pairs and the active load create a trans-conductance amplifier with a very low equivalent trans-conductance. According to some embodiments, the same invention applies to a differential trans-capacitance amplifier.
摘要翻译：根据一些实施例，跨电容放大器在picoAmperes的范围内呈现偏置的输入电流，同时允许大的输出摆幅。跨电容放大器包括运算放大器，反馈电容器，DC偏置电路和运算放大器的非反相输入端的AC接地，以及用于对运算放大器的反相输入进行DC偏置的电路。根据一些实施例，偏置反相输入的电路包括退化差分对的级联。第一对的第一晶体管和最后一对的第二晶体管具有有功负载。差分对的级联和有源负载产生具有非常低的等效反电导的跨导放大器。根据一些实施例，本发明适用于差分跨电容放大器。

9. 发明授权

US08830101B1 Single phase clock D/A converter with built-in data combiner 有权
标题翻译：具有内置数据组合器的单相时钟D / A转换器
公开(公告)号：US08830101B1
公开(公告)日：2014-09-09
申请号：US14058425
申请日：2013-10-21
申请人： Ion E. Opris
发明人： Ion E. Opris
IPC分类号： H03M1/66 , H03M1/06
CPC分类号： H03M1/0614 , H03M1/742
摘要： According to some embodiments, a digital to analog converter comprises an array of input data streams. An array of differential MOS switches are all biased by a common tail current source. A data stream combiner combines and selects at each clock cycle the correct bit. Only one transistor from the switches conducts current at any time. The duration during which a switch conducts current is independent upon the fronts of the bits from the input data streams, thus rendering the switching code independent.
摘要翻译：根据一些实施例，数模转换器包括输入数据流的阵列。一组差分MOS开关全部由公共尾电流源偏置。数据流组合器在每个时钟周期组合并选择正确的位。开关中只有一个晶体管可以随时传导电流。开关导通电流的持续时间独立于来自输入数据流的位的前沿，从而使开关代码独立。

10. 发明授权

US08502581B1 Multi-phase digital phase-locked loop device for pixel clock reconstruction 有权
标题翻译：用于像素时钟重建的多相数字锁相环装置
公开(公告)号：US08502581B1
公开(公告)日：2013-08-06
申请号：US12658366
申请日：2010-02-06
申请人： Ion E. Opris
发明人： Ion E. Opris
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/0995 , H03L7/18 , H03L2207/50
摘要： A reconstruction circuit for the pixel clock in digital display units receiving analog display data uses a multi-phase reference clock and an all digital PLL for clock generation and synchronization to an external sync signal. A phase/frequency detector in the digital PLL uses a multi-phase reference clock to achieve a high resolution of the phase error. The digital PLL control algorithm can be implemented with a single loop and can achieved arbitrary large, externally controlled, phase difference between the generated pixel clock and the input sync signal.
摘要翻译：用于接收模拟显示数据的数字显示单元中的像素时钟的重构电路使用多相参考时钟和全数字PLL来产生和同步到外部同步信号。数字PLL中的相位/频率检测器使用多相参考时钟来实现相位误差的高分辨率。数字PLL控制算法可以用单个环路实现，并且可以实现所产生的像素时钟和输入同步信号之间的任意大的，外部受控的相位差。

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