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1. 发明授权

US08447242B2 Hybrid circuit for a transceiver front-end 有权
标题翻译：收发器前端的混合电路
公开(公告)号：US08447242B2
公开(公告)日：2013-05-21
申请号：US13292501
申请日：2011-11-09
申请人： Jan Roelof Westra , Rudy J. Van De Plassche , Chi-Hung Lin
发明人： Jan Roelof Westra , Rudy J. Van De Plassche , Chi-Hung Lin
IPC分类号： H04B1/44
CPC分类号： H04B1/583
摘要： A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.
摘要翻译：收发器前端提供传输介质和发射器之间以及传输介质和接收器之间的接口。收发器前端包括混合电路，高通滤波器和增益级，允许减少或完全消除缓冲放大器。可以消除缓冲放大器，因为混合电路和/或高通滤波器被适配成使得它们可以彼此直接连接，而不会损失电路性能。此外，高通滤波器和/或增益级也适于直接连接。因此，收发器前端可以使用所有无源组件构建，从而减少或消除多余的发热。

2. 发明授权

US5751236A A/D conversion with folding and interpolation 失效
标题翻译： A / D转换与折叠和插值
公开(公告)号：US5751236A
公开(公告)日：1998-05-12
申请号：US709401
申请日：1996-09-04
申请人： Pieter Vorenkamp , Arnoldus G.W. Venes , Rudy J. Van De Plassche
发明人： Pieter Vorenkamp , Arnoldus G.W. Venes , Rudy J. Van De Plassche
IPC分类号： H03M1/34 , H03M1/20 , H03M1/36 , H03M1/00
CPC分类号： H03M1/204 , H03M1/141
摘要： An A/D converter has an input part IS which provides differential transitions T1 . . . T.sub.x associated with different levels of an analog input signal. An intermediate part IMS of the converter carries out folding operations and interpolation operations on the transitions to thereby obtain a set of bit-determining signals XO . . . XQ. At least one of the folding and interpolation operations is carried out more than once in alternation with the other of such operations. An output part OS produces a digital output signal from the bit-determining signals. Such an A/D converter can be implemented in a cost-efficient manner and may be combined with digital signal processing circuitry. The repetition of at least one of the operations alternately with the other permits the interpolation factor to be increased without necessitating increased complexity of the output part, and the folding factor to be increased without adversely affecting the accuracy of the converter.
摘要翻译： A / D转换器具有提供差分转换T1的输入部分IS。。。 Tx与不同级别的模拟输入信号相关联。转换器的中间部分IMS对转换执行折叠操作和插值操作，从而获得一组位确定信号XO。。。 XQ。折叠和内插操作中的至少一个与另一个这样的操作交替执行多次。输出部分OS从位确定信号产生数字输出信号。这样的A / D转换器可以以成本有效的方式实现，并且可以与数字信号处理电路组合。与其他操作交替地重复操作中的至少一个允许增加内插因子，而不必增加输出部分的复杂性，并且折叠因子将增加而不会不利地影响转换器的精度。

3. 发明授权

US5742203A Gain-controllable amplifier, receiver 失效
标题翻译：增益可控放大器，接收器
公开(公告)号：US5742203A
公开(公告)日：1998-04-21
申请号：US543731
申请日：1995-10-16
申请人： Rudy J. Van De Plassche , Petrus J. G. Van Lieshout
发明人： Rudy J. Van De Plassche , Petrus J. G. Van Lieshout
IPC分类号： H03G3/20 , H03G1/00 , H03G3/10 , H03G3/30 , H03G11/00 , H03G11/08 , H03F3/45
CPC分类号： H03G3/3005 , H03F1/3211 , H03G1/0023 , H03G3/3052
摘要： well as a receiver having low noise and low distortion. These functional units include at least one transadmittance stage having differential transistor pairs coupled in parallel. Gain control is effectuated by varying the unbalance in the differential transistor.
摘要翻译：以及具有低噪声和低失真的接收机。这些功能单元包括具有并联耦合的差分晶体管对的至少一个互导纳级。增益控制通过改变差分晶体管的不平衡来实现。

4. 发明授权

US5886544A Signal processing with sampling 失效
标题翻译：信号处理采样
公开(公告)号：US5886544A
公开(公告)日：1999-03-23
申请号：US708380
申请日：1996-09-04
申请人： Rudy J. Van De Plassche , Arnoldus G. W. Venes
发明人： Rudy J. Van De Plassche , Arnoldus G. W. Venes
IPC分类号： H03M1/12 , H03M1/00 , H03M1/36 , G11C27/02
CPC分类号： H03M1/1245 , H03M1/141 , H03M1/203
摘要： A signal-processing arrangement includes a conversion circuit CONV which converts an input signal Sin into sub-ranging signals Sc(1)..Sc(N) corresponding to different amplitude sub-ranges of the input signal Sin. Each sub-range signal is supplied to a respective one of an array of sampling circuits SC(1)..SC(N) which supplies successive samples thereof to a processing circuit PROC for processing in accordance with operations which may constitute or include A/D conversion. Such an arrangement is particularly suitable for use in a television receiver, multimedia or other video image display apparatus, and various types of disc-players and tape-recorders.
摘要翻译：信号处理装置包括将输入信号Sin转换成对应于输入信号Sin的不同幅度子范围的子范围信号Sc（1）... Sc（N）的转换电路CONV。每个子范围信号被提供给采样电路SC（1）... SC（N）中的相应一个，其提供其连续样本到处理电路PROC，用于根据可构成或包括A / D转换。这种布置特别适用于电视接收机，多媒体或其他视频图像显示装置，以及各种类型的唱盘播放器和录像机。

5. 发明授权

US06362758B1 Combined input circuit for analog to digital conversion 有权
标题翻译：用于模数转换的组合输入电路
公开(公告)号：US06362758B1
公开(公告)日：2002-03-26
申请号：US09244839
申请日：1999-02-02
申请人： Arnoldus G. W. Venes , Rudy J. Van De Plassche
发明人： Arnoldus G. W. Venes , Rudy J. Van De Plassche
IPC分类号： H03M100
CPC分类号： H03M1/14 , H03M1/1245
摘要： An input circuit for, for example, an A/D converter mainly determines the performance of the circuit preceded by the input circuit (A/D converter). To improve the performance of the input circuit and to overcome the problem of high-power dissipation at the same time, the invention proposes the use of a combined sampling means and sub-ranging means as an input circuit.
摘要翻译：用于例如A / D转换器的输入电路主要确定在输入电路（A / D转换器）之前的电路的性能。为了提高输入电路的性能并同时克服高功耗的问题，本发明提出了组合采样装置和子测距装置作为输入电路的使用。

6. 发明授权

US06175269B1 Demodulation unit and method of demodulating a quadrature 失效
标题翻译：解调单元和解调正交的方法
公开(公告)号：US06175269B1
公开(公告)日：2001-01-16
申请号：US09196089
申请日：1998-11-19
申请人： Gerardus C. M. Gielis , Rudy J. Van De Plassche
发明人： Gerardus C. M. Gielis , Rudy J. Van De Plassche
IPC分类号： H03D300
CPC分类号： H03D1/2254 , H03D3/245 , H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0069
摘要： To demodulate a quadrature input signal (Si) (for example, frequency shift) a demodulation unit (DEM) is used, comprising a PLL (P) having a complex mixer (M) and a controlled oscillator (V). Normally, a limiter has to be used to keep the loop gain independent of the amplitude of the quadrature input signal. In the PLL, a divider (DEL) is coupled between the mixer (M) and the oscillator (V) to divide the two mixed components (Sm1, Sm2) of the quadrature signal supplied by the mixer.
摘要翻译：为了解调正交输入信号（Si）（例如，频移），使用解调单元（DEM），其包括具有复合混频器（M）和受控振荡器（V）的PLL（P）。通常，必须使用限幅器来保持环路增益，而不受正交输入信号的幅度的影响。在PLL中，分频器（DEL）耦合在混频器（M）和振荡器（V）之间，以分频由混频器提供的正交信号的两个混合分量（Sm1，Sm2）。

7. 发明授权

US5889822A Signal processor with reduced complexity, and receiver comprising such a signal processor 失效
标题翻译：具有降低的复杂度的信号处理器和包括这种信号处理器的接收器
公开(公告)号：US5889822A
公开(公告)日：1999-03-30
申请号：US704200
申请日：1996-08-28
申请人： Rudy J. Van De Plassche , Gerardus C.M. Gielis
发明人： Rudy J. Van De Plassche , Gerardus C.M. Gielis
IPC分类号： H04L27/22 , G06F7/48 , G06F17/16 , G06F17/17 , H04L27/06 , H04L27/14
CPC分类号： G06F7/4818
摘要： A signal processor has an X-Y rotation circuit and a phase angle control circuit, in the phase angle control circuit, an input phase being approximated by a series of consecutive, in magnitude, decreasing phase angles for forming an output vector by rotation of an input vector over the approximation of the input phase. In the phase angle control circuit, an accuracy of the representation of a phase angle out of the series of phase angles, is dependent on the magnitude of the phase angle, thereby reducing the number of computations in the phase angle control circuit.
摘要翻译：信号处理器具有XY旋转电路和相位角控制电路，在相位角控制电路中，输入相位由一系列连续的大幅度减小的相位角近似，用于通过输入矢量的旋转来形成输出矢量超过输入阶段的近似值。在相位角控制电路中，相位角的一系列相位角的表示的精度取决于相位角的大小，从而减少了相位角控制电路中的计算次数。

8. 发明授权

US5859607A Receiver with digital processing of a phase-splitted input signal 失效
标题翻译：具有数字处理相位分离输入信号的接收器
公开(公告)号：US5859607A
公开(公告)日：1999-01-12
申请号：US802964
申请日：1997-02-21
申请人： Arie J. Leeuwenburgh , Rudy J. Van De Plassche
发明人： Arie J. Leeuwenburgh , Rudy J. Van De Plassche
IPC分类号： H04L27/22 , H03D1/22 , H03D3/00 , H04B1/16 , H03M1/00
CPC分类号： H03D3/007 , H03D1/2245
摘要： In a receiver, both an A/D conversion (ADC) and a phase-split (PSF) is carried out on an input signal (R) to obtain a pair of digital signals (Xd,Yd) which are mutually phase shifted. The pair of digital signals (Xd,Yd) is processed (VSP) as a vectorial signal with a frequency-characteristic which is asymmetrical with respect to zero frequency. In order to make the receiver better suited for relatively low A/D conversion sampling frequencies (Fs), the phase-split (PSF) is carried out prior to the A/D conversion (ADC).
摘要翻译：在接收机中，在输入信号（R）上执行A / D转换（ADC）和相位分离（PSF），以获得相互相移的一对数字信号（Xd，Yd）。该对数字信号（Xd，Yd）被处理（VSP）为具有相对于零频率不对称的频率特性的矢量信号。为了使接收机更适合于较低的A / D转换采样频率（Fs），在A / D转换（ADC）之前执行相位分离（PSF）。

9. 发明授权

US5835047A Folding A/D converter 失效
标题翻译：折叠A / D转换器
公开(公告)号：US5835047A
公开(公告)日：1998-11-10
申请号：US704198
申请日：1996-08-28
申请人： Pieter Vorenkamp , Rudy J. Van De Plassche
发明人： Pieter Vorenkamp , Rudy J. Van De Plassche
IPC分类号： H03M1/14 , H03F3/45 , H03M1/20 , H03M1/36
CPC分类号： H03M1/203 , H03M1/141
摘要： In a folding A/D converter, a comparison part CPM provides a plurality of comparison signals Sc1 . . . Sc9 in response to an input signal Si. The transients in the comparison signals Sc1 . . . Sc9 are mutually shifted and substantially overlap. Because of the overlap, only a relatively small input signal variation is needed to pass all the transients. A limiting part LIM effectively selects portions of the transients. A combining part CBM effectively multiplexes these selected portions into a folding signal Sf. The selection by the limiting part LIM prevents distortion of the folding signal Sf, despite the overlap.
摘要翻译：在折叠A / D转换器中，比较部分CPM提供多个比较信号Sc1。。。 Sc9响应于输入信号Si。比较信号Sc1中的瞬变。。。 Sc9相互偏移并且基本上重叠。由于重叠，只需要相对较小的输入信号变化来传递所有瞬变。限制部分LIM有效地选择部分瞬变。组合部分CBM将这些选择的部分有效地多路复用成折叠信号Sf。限制部分LIM的选择防止折叠信号Sf的失真，尽管重叠。

10. 发明授权

US06643502B1 Multi-standard reception 失效
标题翻译：多标准接待
公开(公告)号：US06643502B1
公开(公告)日：2003-11-04
申请号：US09121576
申请日：1998-07-23
申请人： Rudy J. Van De Plassche , Alphons A. M. L. Bruekers , Gerardus C. M. Gielis
发明人： Rudy J. Van De Plassche , Alphons A. M. L. Bruekers , Gerardus C. M. Gielis
IPC分类号： H04B116
CPC分类号： H04N5/4446 , H04B1/1036 , H04B1/26 , H04N5/4401 , H04N5/46
摘要： In a receiver, a tuner (TUN) converts a reception signal (Srf) to an intermediate-frequency signal (Sif). An adjustable frequency converter (AFRC) converts the intermediate-frequency signal (Sif) to an input signal (Sin) for a filter arrangement (FIL) which is capable of providing various frequency responses (Hfil1, Hfil2) associated with different transmission standards. The adjustable frequency converter (AFRC) and the filter arrangement (FIL) may form part of an integrated receiver-circuit (IRC) suitable for many different transmission standards. The tuner (TUN) may provide the intermediate-frequency signal (Sif) at any one of various different intermediate frequencies (IF1, IF2). For any intermediate frequency (IF1,IF2), the adjustable frequency converter (AFRC) can be adjusted in such a way that the filter arrangement (FIL) receives the input signal (Sin) in a frequency range (FR) which is suitably located with respect to its frequency responses (Hfil1, Hfil2). Thus, the adjustable frequency converter (AFRC) allows the use of any one of various different intermediate frequencies and, therefore, allows the use of relatively cheap standard-specific tuners. Thus, it allows relatively cost-efficient implementations.
摘要翻译：在接收机中，调谐器（TUN）将接收信号（Srf）转换成中频信号（Sif）。可调变频器（AFRC）将中频信号（Sif）转换为能够提供与不同传输标准相关联的各种频率响应（Hfil1，Hfil2）的滤波器装置（FIL）的输入信号（Sin）。可调变频器（AFRC）和滤波器装置（FIL）可以构成适合于许多不同传输标准的集成接收机电路（IRC）的一部分。调谐器（TUN）可以在各种不同的中频（IF1，IF2）中的任何一个处提供中频信号（Sif）。对于任何中频（IF1，IF2），可调节变频器（AFRC），使得滤波器装置（FIL）在频率范围（FR）中接收输入信号（Sin），该频率范围（FR）相对于其频率响应（Hfil1，Hfil2）。因此，可调变频器（AFRC）允许使用各种不同的中频中的任一种，因此允许使用相对便宜的标准特定调谐器。因此，它允许相对成本有效的实现。

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