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1. 发明授权

US08081932B2 Transceiver front-end 有权
标题翻译：收发器前端
公开(公告)号：US08081932B2
公开(公告)日：2011-12-20
申请号：US11400288
申请日：2006-04-10
申请人： Jan Roelof Westra , Rudy J. van de Plassche , Chi-Hung Lin
发明人： Jan Roelof Westra , Rudy J. van de Plassche , Chi-Hung Lin
IPC分类号： H04B1/44
CPC分类号： H04B1/583
摘要： A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.
摘要翻译：收发器前端提供传输介质和发射器之间以及传输介质和接收器之间的接口。收发器前端包括混合电路，高通滤波器和增益级，允许减少或完全消除缓冲放大器。可以消除缓冲放大器，因为混合电路和/或高通滤波器被适配成使得它们可以彼此直接连接，而不会损失电路性能。此外，高通滤波器和/或增益级也适于直接连接。因此，收发器前端可以使用所有无源组件构建，从而减少或消除多余的发热。

2. 发明授权

US07324038B2 Subranging analog to digital converter with multi-phase clock timing 有权
标题翻译：使用多相时钟定时将模数转换器分段
公开(公告)号：US07324038B2
公开(公告)日：2008-01-29
申请号：US10625702
申请日：2003-07-24
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Ruby van de Plassche , Marcel Lugthart
IPC分类号： H03M1/12
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

3. 发明申请

US20120058736A1 Transceiver Front-End 有权
标题翻译：收发器前端
公开(公告)号：US20120058736A1
公开(公告)日：2012-03-08
申请号：US13292501
申请日：2011-11-09
申请人： Jan Roelof Westra , Rudy J. van de Plassche , Chi-Hung Lin
发明人： Jan Roelof Westra , Rudy J. van de Plassche , Chi-Hung Lin
IPC分类号： H04B1/44
CPC分类号： H04B1/583
摘要： A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.
摘要翻译：收发器前端提供传输介质和发射器之间以及传输介质和接收器之间的接口。收发器前端包括混合电路，高通滤波器和增益级，允许减少或完全消除缓冲放大器。可以消除缓冲放大器，因为混合电路和/或高通滤波器被适配成使得它们可以彼此直接连接，而不会损失电路性能。此外，高通滤波器和/或增益级也适于直接连接。因此，收发器前端可以使用所有无源组件构建，从而减少或消除多余的发热。

4. 发明授权

US06501401B2 Means for compensating a data-dependent supply current in an electronic circuit 有权
标题翻译：用于补偿电子电路中数据相关电源电流的装置
公开(公告)号：US06501401B2
公开(公告)日：2002-12-31
申请号：US09962649
申请日：2001-09-25
申请人： Jeroen Michiel Van Den Boom , Jan Roelof Westra , Quino Alexander Sandifort
发明人： Jeroen Michiel Van Den Boom , Jan Roelof Westra , Quino Alexander Sandifort
IPC分类号： H03M106
CPC分类号： H03M1/0678 , H03M1/742
摘要： Electronic circuitry comprising a data processing circuit for processing a digital signal (DS), such as a digital to analog converter (DAC), and a current compensation circuit (CMP). Both the digital to analog converter (DAC) and the current compensation circuit (CMP) are powered by a single power supply (U1). The current taken from the power supply (U1) by the digital to analog converter (DAC) is normally dependent on the digital input signal (DS). This would lead to distortion since the loss-resistances (R11, R12) which are always present in series with the power supply (U1) then feed a data-dependent supply voltage (U2) to the digital to analog converter (DAC). This problem is overcome by the addition of the current compensation circuit (CMP) which is coupled for receiving the digital signal (DS). The current compensation circuit (CMP) is arranged in such a way that the sum of the data-dependent current drawn by the digital to analog converter (DAC) and the data-dependent current drawn by the compensation circuit (CMP) is substantially independent of the data.
摘要翻译：电子电路包括用于处理数字信号（DS）的数据处理电路，例如数模转换器（DAC）和电流补偿电路（CMP）。数模转换器（DAC）和电流补偿电路（CMP）由单个电源（U1）供电。通过数模转换器（DAC）从电源（U1）获取的电流通常取决于数字输入信号（DS）。这将导致失真，因为始终与电源（U1）串联存在的损耗电阻（R11，R12）然后将数据相关电源电压（U2）馈送到数模转换器（DAC）。通过添加用于接收数字信号（DS）的电流补偿电路（CMP）来克服该问题。电流补偿电路（CMP）被布置成使得由数模转换器（DAC）汲取的与数据相关的电流之和与由补偿电路（CMP）汲取的与数据相关的电流之和基本上独立于数据。

5. 发明授权

US06426715B1 Digital to analog converter 有权
标题翻译：数模转换器
公开(公告)号：US06426715B1
公开(公告)日：2002-07-30
申请号：US09698762
申请日：2000-10-27
申请人： Jan Roelof Westra , Anne Johan Annema
发明人： Jan Roelof Westra , Anne Johan Annema
IPC分类号： H03M106
CPC分类号： H03M1/0665 , H03M1/1205 , H03M1/747
摘要： A digital to analog converter for a multibit digital input signal has a set of conversion elements for the positive signal excursions and a set of conversion elements for the negative signal excursions. In each set the conversion elements are selected according to a dynamic element matching algorithm. To improve the mismatch-noise shaping of these algorithms, excess conversion elements may be additionally selected.
摘要翻译：用于多位数字输入信号的数模转换器具有用于正信号偏移的一组转换元件和用于负信号偏移的一组转换元件。在每个集合中，根据动态元素匹配算法选择转换元素。为了改善这些算法的失配噪声整形，可以另外选择多余的转换元件。

6. 发明授权

US07551035B2 Fast converter for crossing voltage domains 有权
标题翻译：用于交叉电压域的快速转换器
公开(公告)号：US07551035B2
公开(公告)日：2009-06-23
申请号：US11508966
申请日：2006-08-24
申请人： Jan Roelof Westra , Franciscus Maria Leonardus van der Goes , Erol Arslan
发明人： Jan Roelof Westra , Franciscus Maria Leonardus van der Goes , Erol Arslan
IPC分类号： H03F3/04
CPC分类号： H03F3/343
摘要： A voltage domain crossing circuit and method are disclosed. In one embodiment, the voltage domain crossing circuit comprises an AC coupling component, a DC biasing component and a high voltage output amplifier. The AC coupling component receives an input low voltage signal and AC couples and splits the signal into two voltages. The two voltages are then DC biased to a predetermined bias voltage using the DC biasing component. The high voltage output amplifier then amplifies the biased voltages in the high voltage domain yielding a signal in the high voltage domain. Other embodiments of the voltage domain crossing circuit and method are also disclosed.
摘要翻译：公开了一种电压域交叉电路和方法。在一个实施例中，电压域交叉电路包括AC耦合部件，DC偏置部件和高压输出放大器。 AC耦合组件接收输入低电压信号，并且AC将信号分离成两个电压。然后使用DC偏置组件将两个电压直流偏置到预定的偏置电压。然后，高电压输出放大器放大高电压域中的偏置电压，产生高电压域中的信号。还公开了电压域交叉电路和方法的其他实施例。

7. 发明申请

US20070182605A1 Fast converter for crossing voltage domains 有权
标题翻译：用于交叉电压域的快速转换器
公开(公告)号：US20070182605A1
公开(公告)日：2007-08-09
申请号：US11508966
申请日：2006-08-24
申请人： Jan Roelof Westra , Franciscus Maria Leonardus van der Goes , Erol Arslan
发明人： Jan Roelof Westra , Franciscus Maria Leonardus van der Goes , Erol Arslan
IPC分类号： H03M1/06
CPC分类号： H03F3/343
摘要： A voltage domain crossing circuit and method are disclosed. In one embodiment, the voltage domain crossing circuit comprises an AC coupling component, a DC biasing component and a high voltage output amplifier. The AC coupling component receives an input low voltage signal and AC couples and splits the signal into two voltages. The two voltages are then DC biased to a predetermined bias voltage using the DC biasing component. The high voltage output amplifier then amplifies the biased voltages in the high voltage domain yielding a signal in the high voltage domain. Other embodiments of the voltage domain crossing circuit and method are also disclosed.
摘要翻译：公开了一种电压域交叉电路和方法。在一个实施例中，电压域交叉电路包括AC耦合部件，DC偏置部件和高压输出放大器。 AC耦合组件接收输入低电压信号，并且AC将信号分离成两个电压。然后使用DC偏置组件将两个电压直流偏置到预定的偏置电压。然后，高电压输出放大器放大高电压域中的偏置电压，产生高电压域中的信号。还公开了电压域交叉电路和方法的其他实施例。

8. 发明授权

US06653966B1 Subranging analog to digital converter with multi-phase clock timing 有权
标题翻译：使用多相时钟定时将模数转换器分段
公开(公告)号：US06653966B1
公开(公告)日：2003-11-25
申请号：US10359201
申请日：2003-02-06
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward , Jan Roelof Westra , Rudy van de Plassche , Marcel Lugthart
IPC分类号： H03M100
CPC分类号： H03M1/146 , H03K17/04106 , H03M1/204 , H03M1/365
摘要： An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
摘要翻译： N位模数转换器包括参考梯形图，连接到输入电压的跟踪和保持放大器，在其输入处连接到粗略电容器的粗略ADC放大器，并具有由第一时钟控制的粗略ADC复位开关两相时钟的相位，精细ADC放大器在其输入端连接到精细电容器，并具有由两相时钟的第二时钟相位控制的精细ADC复位开关，开关矩阵从第二时钟相位选择电压子范围参考梯形图，用于基于粗ADC放大器的输出的精细ADC放大器使用，并且其中粗电容器在第一时钟相位期间被充电到粗略的参考梯形电压，并且在第二时钟相位期间连接到T / H输出其中精细电容器在第一时钟相位期间连接到电压子范围，并且在第二时钟相位期间连接到T / H输出;以及编码器，其将粗略和精细ADC放大器的输出转换为Nb 它输出。

9. 发明授权

US08447242B2 Hybrid circuit for a transceiver front-end 有权
标题翻译：收发器前端的混合电路
公开(公告)号：US08447242B2
公开(公告)日：2013-05-21
申请号：US13292501
申请日：2011-11-09
申请人： Jan Roelof Westra , Rudy J. Van De Plassche , Chi-Hung Lin
发明人： Jan Roelof Westra , Rudy J. Van De Plassche , Chi-Hung Lin
IPC分类号： H04B1/44
CPC分类号： H04B1/583
摘要： A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.
摘要翻译：收发器前端提供传输介质和发射器之间以及传输介质和接收器之间的接口。收发器前端包括混合电路，高通滤波器和增益级，允许减少或完全消除缓冲放大器。可以消除缓冲放大器，因为混合电路和/或高通滤波器被适配成使得它们可以彼此直接连接，而不会损失电路性能。此外，高通滤波器和/或增益级也适于直接连接。因此，收发器前端可以使用所有无源组件构建，从而减少或消除多余的发热。

10. 发明授权

US07098829B2 Digital to analog conversion 有权
标题翻译：数模转换
公开(公告)号：US07098829B2
公开(公告)日：2006-08-29
申请号：US10511974
申请日：2003-03-19
申请人： Jan Roelof Westra
发明人： Jan Roelof Westra
IPC分类号： H03M1/66
CPC分类号： H03K17/04106 , H03K17/693
摘要： A unit cell for a digital to analog conversion circuit that includes a current source (CS); a first data switch (S1) coupled to the current source (CS); a second data switch (S2) coupled to the current source (CS); a first phase switch (Phi1) coupled between the current source (CS) and the first data switch (S1); a second phase switch (Phi2) coupled between the current source (CS) and the second data switch (S2); a controller arranged to switch between the first (Phi1) and second (Phi2) phase switches in a Break Before Make alternating sequence, and to switch the first (S1) and second (S2) data switches in a Make Before Break sequence. A digital to analog convener circuit constructed using unit cells according to the invention is more area and power efficient than the previously known circuit because it uses only one current source, yet it succeeds in preventing short-circuit error currents between the outputs and solves the problems caused by pulse asymmetry and the influence of switch-charge injection, and provides more linear and better quality output signals.
摘要翻译：一种用于数模转换电路的单元，包括电流源（CS）; 耦合到电流源（CS）的第一数据开关（S1）; 耦合到电流源（CS）的第二数据开关（S 2）; 耦合在电流源（CS）和第一数据开关（S1）之间的第一相位开关（Phi 1）; 耦合在电流源（CS）和第二数据开关（S 2）之间的第二相位开关（Phi2）; 控制器，其布置成在进行交替间隔之前在第一（Phi 1）和第二（Phi 2）相位开关之间切换，并且在第一（S1）和第二（S2）数据开关中断序列。使用根据本发明的单元单元构造的数模转换器电路比以前已知的电路更具面积和功率效率，因为它仅使用一个电流源，但它成功地防止了输出之间的短路误差电流并解决了这些问题引起脉冲不对称和开关电荷注入的影响，并提供更线性和更好质量的输出信号。

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