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1. 发明授权

US08081932B2 Transceiver front-end 有权
标题翻译：收发器前端
公开(公告)号：US08081932B2
公开(公告)日：2011-12-20
申请号：US11400288
申请日：2006-04-10
申请人： Jan Roelof Westra , Rudy J. van de Plassche , Chi-Hung Lin
发明人： Jan Roelof Westra , Rudy J. van de Plassche , Chi-Hung Lin
IPC分类号： H04B1/44
CPC分类号： H04B1/583
摘要： A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.
摘要翻译：收发器前端提供传输介质和发射器之间以及传输介质和接收器之间的接口。收发器前端包括混合电路，高通滤波器和增益级，允许减少或完全消除缓冲放大器。可以消除缓冲放大器，因为混合电路和/或高通滤波器被适配成使得它们可以彼此直接连接，而不会损失电路性能。此外，高通滤波器和/或增益级也适于直接连接。因此，收发器前端可以使用所有无源组件构建，从而减少或消除多余的发热。

2. 发明授权

US5751236A A/D conversion with folding and interpolation 失效
标题翻译： A / D转换与折叠和插值
公开(公告)号：US5751236A
公开(公告)日：1998-05-12
申请号：US709401
申请日：1996-09-04
申请人： Pieter Vorenkamp , Arnoldus G.W. Venes , Rudy J. Van De Plassche
发明人： Pieter Vorenkamp , Arnoldus G.W. Venes , Rudy J. Van De Plassche
IPC分类号： H03M1/34 , H03M1/20 , H03M1/36 , H03M1/00
CPC分类号： H03M1/204 , H03M1/141
摘要： An A/D converter has an input part IS which provides differential transitions T1 . . . T.sub.x associated with different levels of an analog input signal. An intermediate part IMS of the converter carries out folding operations and interpolation operations on the transitions to thereby obtain a set of bit-determining signals XO . . . XQ. At least one of the folding and interpolation operations is carried out more than once in alternation with the other of such operations. An output part OS produces a digital output signal from the bit-determining signals. Such an A/D converter can be implemented in a cost-efficient manner and may be combined with digital signal processing circuitry. The repetition of at least one of the operations alternately with the other permits the interpolation factor to be increased without necessitating increased complexity of the output part, and the folding factor to be increased without adversely affecting the accuracy of the converter.
摘要翻译： A / D转换器具有提供差分转换T1的输入部分IS。。。 Tx与不同级别的模拟输入信号相关联。转换器的中间部分IMS对转换执行折叠操作和插值操作，从而获得一组位确定信号XO。。。 XQ。折叠和内插操作中的至少一个与另一个这样的操作交替执行多次。输出部分OS从位确定信号产生数字输出信号。这样的A / D转换器可以以成本有效的方式实现，并且可以与数字信号处理电路组合。与其他操作交替地重复操作中的至少一个允许增加内插因子，而不必增加输出部分的复杂性，并且折叠因子将增加而不会不利地影响转换器的精度。

3. 发明授权

US4831379A Complementary voltage interpolation circuit 失效
标题翻译：互补电压内插电路
公开(公告)号：US4831379A
公开(公告)日：1989-05-16
申请号：US96793
申请日：1987-09-14
申请人： Rudy J. van de Plassche
发明人： Rudy J. van de Plassche
IPC分类号： H03M1/12 , G06G7/30 , H03M1/14 , H03M1/20 , H03M1/36
CPC分类号： H03M1/205 , G06G7/30 , H03M1/141
摘要： The invention centers around a system for interpolating between multiple pairs of main complementary signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is done with two strings (12) of a selected number of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.NO -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. The interpolated signals are taken from other pairs of corresponding nodes along the strings. The interpolation system is particularly suitable for use in an analog-to-digital converter of the folding type.
摘要翻译：本发明围绕用于在多对主互补信号之间进行内插以产生另外的互补信号对的系统。输入电路（10）提供主信号。内插使用选定数量的阻抗元件（R0-RN-1和RNO-RNN-1）的两个串（12）完成。每对主信号被提供给沿着串的一对相应的节点。内插信号是沿着串的其他对相应节点取的。插值系统特别适用于折叠型的模数转换器。

4. 发明授权

US4737766A Code converter with complementary output voltages 失效
标题翻译：具有互补输出电压的代码转换器
公开(公告)号：US4737766A
公开(公告)日：1988-04-12
申请号：US907349
申请日：1986-09-12
申请人： Rudy J. van de Plassche
发明人： Rudy J. van de Plassche
IPC分类号： H03M1/12 , H03M1/00
CPC分类号： H03M1/368 , H03M1/141
摘要： A double-ended code converter (10) contains three or more like-configured amplifiers (T.sub.O -T.sub.M+1). Each has a first flow electrode (E1), a second flow electrode (E2), and a control electrode (CE) for receiving a signal to control charge carriers moving from the first electrode to the second. The first electrodes are coupled to a circuit supply (12) which may be a current source or a voltage supply. The second electrodes are selectively coupled to one or the other of a pair of lines (L.sub.B and L.sub.BN) which are coupled to respective load elements (14.sub.B and 14.sub.BN) to provide a pair of complementary signals (V.sub.B and V.sub.BN).
摘要翻译：双端码转换器（10）包含三个或更多个相似配置的放大器（TO-TM + 1）。每个具有第一流动电极（E1），第二流动电极（E2）和控制电极（CE），用于接收控制从第一电极移动到第二电极的电荷载流子的信号。第一电极耦合到可以是电流源或电压源的电路电源（12）。第二电极被选择性地耦合到一对线（LB和LBN）中的一个或另一个，耦合到相应的负载元件（14B和14BN）以提供一对互补信号（VB和VBN）。

5. 发明授权

US4555673A Differential amplifier with rail-to-rail input capability and controlled transconductance 失效
标题翻译：具有轨到轨输入能力和受控跨导的差分放大器
公开(公告)号：US4555673A
公开(公告)日：1985-11-26
申请号：US602231
申请日：1984-04-19
申请人： Johan H. Huijsing , Rudy J. van de Plassche
发明人： Johan H. Huijsing , Rudy J. van de Plassche
IPC分类号： H03F3/45
CPC分类号： H03F3/45219 , H03F3/45085 , H03F3/45121 , H03F3/45183 , H03F3/4556 , H03F3/45708
摘要： A differential amplifier operable between a pair of supply voltages that define a rail-to-rail supply range contains a pair of differential portions (20 and 22) that together provide representative signal amplification across the supply range, although neither differential portion individually does so. A current control (24) regulates operating currents (I.sub.N and I.sub.p) for the differential portions in such a way that the amplifier transconductance can be controlled in a desired manner as the common-mode part (V.sub.CM) of the amplifier input signal (V.sub.I+ and V.sub.I-) varies across the supply range. The transconductance is typically controlled to be largely constant. A summing circuit (26) selectively combines internal currents (I.sub.A, I.sub.B, I.sub.C, and I.sub.D) from the differential portions to generate at least one output signal (I.sub.O+ and I.sub.O-) representative of the input signal.
摘要翻译：限定轨至轨电源范围的一对电源电压之间可操作的差分放大器包含一对差分部分（20和22），这些差分部分（20和22）在整个电源范围内提供代表性的信号放大，尽管两个差分部分都不相同。电流控制（24）调节差分部分的工作电流（IN和Ip），使得放大器跨导可以以期望的方式被控制，作为放大器输入信号的共模部分（VCM）（VI +和 VI-）在供应范围内不同。跨导通常被控制在很大程度上恒定。求和电路（26）选择性地组合来自差分部分的内部电流（IA，IB，IC和ID）以产生表示输入信号的至少一个输出信号（IO +和IO-）。

6. 发明授权

US4490714A Digital-to-analog converter for bipolar signals 失效
标题翻译：用于双极性信号的数模转换器
公开(公告)号：US4490714A
公开(公告)日：1984-12-25
申请号：US576988
申请日：1984-02-06
申请人： Rudy J. van de Plassche , Eise C. Dijkmans
发明人： Rudy J. van de Plassche , Eise C. Dijkmans
IPC分类号： H03M1/80 , H03M1/00 , H03K13/02
CPC分类号： H03M1/0607
摘要： In a digital-to-analog converter for bipolar signals all the bits change when the signals pass through the zero level. This results in a poor signal-to-noise ratio owing the small signal and the large noise contribution by the switching transients. The invention proposes to add a digital number to or subtract it from the digital input signal as an offset. As a result of this, the switching point is shifted towards a higher amplitude, which improves the signal-to-noise ratio and the distortion in the case of digital audio signals.
摘要翻译：在双极性信号的数模转换器中，当信号通过零电平时，所有位都会发生变化。这导致由于小信号和由开关瞬变引起的大的噪声贡献而导致的较差的信噪比。本发明提出将数字数字作为偏移量从数字输入信号中加或减。结果，切换点向较高幅度移动，这提高了数字音频信号的信噪比和失真。

7. 发明授权

US08447242B2 Hybrid circuit for a transceiver front-end 有权
标题翻译：收发器前端的混合电路
公开(公告)号：US08447242B2
公开(公告)日：2013-05-21
申请号：US13292501
申请日：2011-11-09
申请人： Jan Roelof Westra , Rudy J. Van De Plassche , Chi-Hung Lin
发明人： Jan Roelof Westra , Rudy J. Van De Plassche , Chi-Hung Lin
IPC分类号： H04B1/44
CPC分类号： H04B1/583
摘要： A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.
摘要翻译：收发器前端提供传输介质和发射器之间以及传输介质和接收器之间的接口。收发器前端包括混合电路，高通滤波器和增益级，允许减少或完全消除缓冲放大器。可以消除缓冲放大器，因为混合电路和/或高通滤波器被适配成使得它们可以彼此直接连接，而不会损失电路性能。此外，高通滤波器和/或增益级也适于直接连接。因此，收发器前端可以使用所有无源组件构建，从而减少或消除多余的发热。

8. 发明授权

US5886544A Signal processing with sampling 失效
标题翻译：信号处理采样
公开(公告)号：US5886544A
公开(公告)日：1999-03-23
申请号：US708380
申请日：1996-09-04
申请人： Rudy J. Van De Plassche , Arnoldus G. W. Venes
发明人： Rudy J. Van De Plassche , Arnoldus G. W. Venes
IPC分类号： H03M1/12 , H03M1/00 , H03M1/36 , G11C27/02
CPC分类号： H03M1/1245 , H03M1/141 , H03M1/203
摘要： A signal-processing arrangement includes a conversion circuit CONV which converts an input signal Sin into sub-ranging signals Sc(1)..Sc(N) corresponding to different amplitude sub-ranges of the input signal Sin. Each sub-range signal is supplied to a respective one of an array of sampling circuits SC(1)..SC(N) which supplies successive samples thereof to a processing circuit PROC for processing in accordance with operations which may constitute or include A/D conversion. Such an arrangement is particularly suitable for use in a television receiver, multimedia or other video image display apparatus, and various types of disc-players and tape-recorders.
摘要翻译：信号处理装置包括将输入信号Sin转换成对应于输入信号Sin的不同幅度子范围的子范围信号Sc（1）... Sc（N）的转换电路CONV。每个子范围信号被提供给采样电路SC（1）... SC（N）中的相应一个，其提供其连续样本到处理电路PROC，用于根据可构成或包括A / D转换。这种布置特别适用于电视接收机，多媒体或其他视频图像显示装置，以及各种类型的唱盘播放器和录像机。

9. 发明授权

US4870417A Error correction circuit suitable for thermometer or circular code 失效
标题翻译：纠错电路适用于温度计或循环码
公开(公告)号：US4870417A
公开(公告)日：1989-09-26
申请号：US155402
申请日：1988-02-12
申请人： Rudy J. van de Plassche , Peter G. Baltus
发明人： Rudy J. van de Plassche , Peter G. Baltus
IPC分类号： G06F11/08 , H03M1/36 , H03M7/16 , H03M13/00
CPC分类号： H03M1/0809 , H03M13/00 , H03M7/165 , H03M1/0646 , H03M1/365
摘要： An error correction circuit employs a digital averaging technique to overcome transition bit errors in a plurality of original binary bits ideally arranged as a thermometer or circular code. The circuit first generates a like plurality of intermediate signals respectively corresponding to the original bits. Each intermediate signal varies according to a weighted analog summation of a specified odd number of consecutive original bits centered about the corresponding bit. The circuit then compares the intermediate signals with corresponding further signals to produce a corrected code.

10. 发明授权

US4587443A Auto-zero sample and hold circuit 失效
标题翻译：自动归零采样保持电路
公开(公告)号：US4587443A
公开(公告)日：1986-05-06
申请号：US644744
申请日：1984-08-27
申请人： Rudy J. van de Plassche
发明人： Rudy J. van de Plassche
IPC分类号： G11C27/02 , H03K7/02
CPC分类号： G11C27/026
摘要： A sample and hold circuit contains a pair of differential amplifiers (A1 and A2) switchably arranged in series. The circiut input signal (V.sub.IN) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) provides the circuit output signal (V.sub.OUT) during hold. Switching circuitry (S1, S2, and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.
摘要翻译：采样和保持电路包含一对串联可切换排列的差分放大器（A1和A2）。采样期间的循环输入信号（VIN）被提供给耦合到存储电容器（C）的第一放大器（A1）。第二放大器（A2）在保持期间提供电路输出信号（VOUT）。开关电路（S1，S2和S3）使得输入和输出信号在第一放大器中经历相同的传递函数。因此第一放大器的电压偏移从输出信号中消除，而第二放大器的电压偏移的影响急剧减小，从而提供优异的自动归零。

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