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1. 发明申请

US20080266938A1 MAGNETORESISTIVE DEVICE AND METHOD OF PACKAGING SAME 有权
标题翻译：磁性装置及其包装方法
公开(公告)号：US20080266938A1
公开(公告)日：2008-10-30
申请号：US11739625
申请日：2007-04-24
申请人： Jaynal A. Molla , Eric J. Salter
发明人： Jaynal A. Molla , Eric J. Salter
IPC分类号： G11C11/02 , G11C7/02 , H01L21/00 , H01L43/12
CPC分类号： G11C11/16 , G11C5/02 , H01L23/552 , H01L24/48 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2924/00014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.
摘要翻译：磁阻存储器件20包括具有磁敏材料50的模具24和38.封装磁阻存储器件20的方法64需要将管芯24耦合到衬底22上，从而在管芯上的焊盘32之间形成互连52 24连接到与模具24间隔开的连接位置54.磁屏蔽36在形成互连52之后结合到模具24的顶表面30.模具38附接到磁屏蔽36，互连56形成在模具38上的接合焊盘44到与模具38间隔开的连接部位58，并且在形成互连56之后，磁屏蔽件48粘附到模具38。

2. 发明授权

US07829980B2 Magnetoresistive device and method of packaging same 有权
标题翻译：磁阻装置及其包装方法
公开(公告)号：US07829980B2
公开(公告)日：2010-11-09
申请号：US11739625
申请日：2007-04-24
申请人： Jaynal A. Molla , Eric J. Salter
发明人： Jaynal A. Molla , Eric J. Salter
IPC分类号： H01L23/552
CPC分类号： G11C11/16 , G11C5/02 , H01L23/552 , H01L24/48 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2924/00014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.
摘要翻译：磁阻存储器件20包括具有磁敏材料50的模具24和38.封装磁阻存储器件20的方法64需要将管芯24耦合到衬底22上，从而在管芯上的焊盘32之间形成互连52 24连接到与模具24间隔开的连接位置54.磁屏蔽36在形成互连52之后结合到模具24的顶表面30.模具38附接到磁屏蔽36，互连56形成在模具38上的接合焊盘44到与模具38间隔开的连接部位58，并且在形成互连56之后，磁屏蔽件48粘附到模具38。

3. 发明申请

US20080116535A1 Methods and apparatus for a dual-metal magnetic shield structure 有权
标题翻译：双金属磁屏蔽结构的方法和装置
公开(公告)号：US20080116535A1
公开(公告)日：2008-05-22
申请号：US11602639
申请日：2006-11-21
申请人： Jaynal A. Molla , Gregory W. Grynkewich , Eric J. Salter
发明人： Jaynal A. Molla , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： H01L29/82 , H01L23/544 , H01L21/60
CPC分类号： H01L23/552 , G11C11/16 , H01L43/08 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.
摘要翻译：用于屏蔽半导体部件（例如，磁阻随机存取存储器或“MRAM”）的电磁场敏感区域的屏蔽结构包括形成在屏蔽层上的半导体器件上的应力消除层（例如，电镀Ni）基本上对应于电磁场敏感区域的磁屏蔽层（例如，电镀的PERMALLOY或MUMETAL层），其机械耦合到屏蔽区域内的应力消除层，其中磁屏蔽层具有应力条件，与应力消除层的基本相反。

4. 发明授权

US07598596B2 Methods and apparatus for a dual-metal magnetic shield structure 有权
标题翻译：双金属磁屏蔽结构的方法和装置
公开(公告)号：US07598596B2
公开(公告)日：2009-10-06
申请号：US11602639
申请日：2006-11-21
申请人： Jaynal A. Molla , Gregory W. Grynkewich , Eric J. Salter
发明人： Jaynal A. Molla , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： H01L23/552 , H01L21/00 , H01L21/8246
CPC分类号： H01L23/552 , G11C11/16 , H01L43/08 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.
摘要翻译：用于屏蔽半导体部件（例如，磁阻随机存取存储器或“MRAM”）的电磁场敏感区域的屏蔽结构包括形成在屏蔽层上的半导体器件上的应力消除层（例如，电镀Ni）基本上对应于电磁场敏感区域的磁屏蔽层（例如，电镀的PERMALLOY或MUMETAL层），其机械耦合到屏蔽区域内的应力消除层，其中磁屏蔽层具有应力条件，与应力消除层的基本相反。

5. 发明申请

US20080205122A1 MRAM MEMORY CONDITIONING 失效
标题翻译： MRAM内存条件
公开(公告)号：US20080205122A1
公开(公告)日：2008-08-28
申请号：US11678346
申请日：2007-02-23
申请人： Eric J. Salter , Mark F. Deherrera , Thomas H. Lee
发明人： Eric J. Salter , Mark F. Deherrera , Thomas H. Lee
IPC分类号： G11C11/02
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.
摘要翻译：根据示例性实施例，一种方法（500）包括将磁场施加到磁隧道结（MTJ）位的阵列，所述磁场的大小足以消除由MTJ中的一个所展现的中间状态位，而不会导致MTJ位中的其他位发展到中间状态。

6. 发明授权

US06252795B1 Programmable resistive circuit using magnetoresistive memory technology 失效
标题翻译：使用磁阻存储器技术的可编程电阻电路
公开(公告)号：US06252795B1
公开(公告)日：2001-06-26
申请号：US09675203
申请日：2000-09-29
申请人： John P. Hansen , Eric J. Salter
发明人： John P. Hansen , Eric J. Salter
IPC分类号： G11C1100
CPC分类号： G11C11/5607 , G11C11/14 , G11C11/15
摘要： A programmable resistive circuit using magnetoresistive memory elements incorporated into one or more programmable segments coupled together between first and second terminals. Each segment includes at least one magnetoresistive memory element and at least one control input to select its state. The resistive circuit further includes select logic coupled to the control inputs of each segment to achieve a programmed resistance. A source signal is applied to the resistive circuit to develop an output signal that is a combination of signals developed by each of the memory elements in the resistive circuit. Bypass logic or switch devices may be included to selectively bypass or remove one or more segments. Each segment may include any combination of series and parallel coupled memory elements. The programmable segments may form a successive configuration to enable programming of progressive resistive values. The progressive resistive values may be linear and the successive configuration may be binary. A programmable current source is achieved by providing a voltage source in which the current is a combination of current signals developed by each of the memory elements in the resistive circuit. A programmable voltage source is achieved by forming first and second resistive circuits on either side of a voltage junction terminal and by applying a voltage source across both resistive circuits. The total resistance across the resistive circuits may be kept constant for each of multiple programmable voltages.
摘要翻译：一种可编程电阻电路，其使用结合到在第一和第二端子之间耦合在一起的一个或多个可编程段的磁阻存储元件。每个段包括至少一个磁阻存储元件和至少一个控制输入以选择其状态。电阻电路还包括耦合到每个段的控制输入的选择逻辑以实现编程电阻。源信号被施加到电阻电路以产生作为由电阻电路中的每个存储器元件开发的信号的组合的输出信号。可以包括旁路逻辑或开关器件以选择性地绕过或去除一个或多个段。每个段可以包括串联和并联耦合的存储器元件的任何组合。可编程段可以形成连续配置，以使得能够对渐进电阻值进行编程。渐进电阻值可以是线性的，并且连续配置可以是二进制的。通过提供电压源来实现可编程电流源，其中电流是由电阻电路中的每个存储器元件开发的电流信号的组合。可编程电压源通过在电压结端子的任一侧上形成第一和第二电阻电路并且通过在两个电阻电路上施加电压来实现。跨多个可编程电压的电阻电路两端的总电阻可以保持恒定。

7. 发明授权

US07324369B2 MRAM embedded smart power integrated circuits 有权
标题翻译： MRAM嵌入式智能电源集成电路
公开(公告)号：US07324369B2
公开(公告)日：2008-01-29
申请号：US11170874
申请日：2005-06-30
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： G11C11/00
CPC分类号： G11C11/1659 , H01F10/3254
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。制造工艺技术是具有前端工艺和后端工艺的模块化工艺。在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

8. 发明授权

US06225933B1 Digital to analog converter using magnetoresistive memory technology 失效
标题翻译：使用磁阻存储器技术的数模转换器
公开(公告)号：US06225933B1
公开(公告)日：2001-05-01
申请号：US09675181
申请日：2000-09-29
申请人： Eric J. Salter , John P. Hansen
发明人： Eric J. Salter , John P. Hansen
IPC分类号： H03M166
CPC分类号： H03M1/685 , G11C11/5607 , H03M1/74 , H03M1/808
摘要： A digital to analog converter using a memory array of multi-state magnetoresistive memory elements in which a number of the memory elements are programmed in proportion to a received digital input. A source selectively applies a reference signal to the programmed memory elements in the memory array, and an analog output signal is developed at an output terminal that combines signals developed by each of the memory elements. The reference signal may be a voltage or current signal, where the output signal is a current or voltage signal, respectively. The memory array may include column and row drive circuitry and control logic that controls the drive circuitry to program the memory array and assert the reference signal to develop the output signal. The control logic may be configured to program the memory array in successive steps by first programming one or more complete memory lines and then programming one or more partial memory lines. Alternatively, the control logic and the drive circuitry may be configured to program the memory array in a single write operation. Signal processing circuitry may be provided to detect changes or threshold conditions in the memory array.
摘要翻译：一种使用多状态磁阻存储器元件的存储器阵列的数模转换器，其中多个存储器元件与接收到的数字输入成比例地被编程。源选择性地将参考信号施加到存储器阵列中的编程存储器元件，并且在组合由每个存储器元件开发的信号的输出端子处产生模拟输出信号。参考信号可以是电压或电流信号，其中输出信号分别是电流或电压信号。存储器阵列可以包括列和行驱动电路和控制逻辑，其控制驱动电路对存储器阵列进行编程并且断言参考信号以产生输出信号。控制逻辑可以被配置为通过首先编程一个或多个完整的存储器线，然后对一个或多个部分存储器线进行编程，以连续的步骤对存储器阵列进行编程。或者，控制逻辑和驱动电路可以被配置为在单个写入操作中对存储器阵列进行编程。可以提供信号处理电路以检测存储器阵列中的变化或阈值条件。

9. 发明授权

US07432150B2 Method of manufacturing a magnetoelectronic device 有权
标题翻译：制造磁电子器件的方法
公开(公告)号：US07432150B2
公开(公告)日：2008-10-07
申请号：US11351610
申请日：2006-02-10
申请人： Mark A. Durlam , Gloria J. Kerszykowski , Nicholas D. Rizzo , Eric J. Salter , Loren J. Wise
发明人： Mark A. Durlam , Gloria J. Kerszykowski , Nicholas D. Rizzo , Eric J. Salter , Loren J. Wise
IPC分类号： H01L21/8234 , H01L21/8244
CPC分类号： H01L43/12
摘要： A method of manufacturing a magnetoelectronic device includes providing an electrically conducting material and an electrically insulating material adjacent to at least a portion of the electrically conducting material, and implanting a magnetic material into the electrically insulating material. The magnetic material increases the magnetic permeability of the electrically insulating material. The implant may be a blanket or a targeted implant.
摘要翻译：制造磁电子器件的方法包括提供导电材料和与导电材料的至少一部分相邻的电绝缘材料，以及将磁性材料注入到电绝缘材料中。磁性材料增加了电绝缘材料的磁导率。植入物可以是毯子或靶向植入物。

10. 发明授权

US07264985B2 Passive elements in MRAM embedded integrated circuits 有权
标题翻译： MRAM嵌入式集成电路中的被动元件
公开(公告)号：US07264985B2
公开(公告)日：2007-09-04
申请号：US11217146
申请日：2005-08-31
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： H01L21/00
CPC分类号： H01L27/228
摘要： An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.
摘要翻译：集成电路器件（300）包括形成在衬底（308）上的衬底（301）和MRAM架构（314）。 MRAM架构（314）包括形成在基板（301）上的MRAM电路（318）。和耦合到并形成在MRAM电路（318）上方的MRAM单元（316）。另外，与MRAM单元（316）结合形成无源器件（320）。无源器件（320）可以是一个或多个电阻器和一个或多个电容器。 MRAM架构（314）和无源器件（320）的并发制造有助于在衬底（404,504）的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

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