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1. 发明授权

US09105323B2 Memory device power managers and methods 有权
标题翻译：内存设备电源管理器和方法
公开(公告)号：US09105323B2
公开(公告)日：2015-08-11
申请号：US12359039
申请日：2009-01-23
申请人： Joe M. Jeddeloh
发明人： Joe M. Jeddeloh
IPC分类号： G06F1/26 , G06F1/32 , G06F13/00 , G11C5/14 , G11C5/02
CPC分类号： G11C7/1012 , G06F1/3225 , G06F1/3275 , G06F13/4022 , G11C5/02 , G11C5/147 , G11C5/148 , G11C7/1072 , Y02D10/14 , Y02D10/151
摘要： Memory devices and methods are described that include a stack of memory dies and an attached logic die. Method and devices described provide for power management of portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
摘要翻译：描述了包括存储器管芯堆叠和附加的逻辑管芯的存储器件和方法。所描述的方法和设备提供了对存储器管芯堆叠的部分的功率管理。公开了附加设备，系统和方法。

2. 发明授权

US08806131B2 Multi-serial interface stacked-die memory architecture 有权
标题翻译：多串行接口堆叠存储器架构
公开(公告)号：US08806131B2
公开(公告)日：2014-08-12
申请号：US13179156
申请日：2011-07-08
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： H04L12/28 , H04L12/56 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F2213/16 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
摘要翻译：本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

3. 发明授权

US08619481B2 Switched interface stacked-die memory architecture 有权
标题翻译：交换式接口堆叠式存储器架构
公开(公告)号：US08619481B2
公开(公告)日：2013-12-31
申请号：US13595294
申请日：2012-08-27
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G06F13/1668 , G06F13/4239 , G11C5/02 , G11C7/10 , G11C8/10 , G11C29/04 , Y02B70/123 , Y02B70/126 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
摘要翻译：本文公开的系统和方法包括可以接收包括所请求的存储器地址的存储器请求的那些，并且可以将存储器请求直接发送到与堆叠的存储器存储库相关联的地址解码器，而不知道是否需要修复地址。如果对存储器请求的后续分析显示需要修复地址，则可以暂停所请求的存储器地址的进程内解码并启动修复地址的解码。

4. 发明申请

US20130003473A1 STACKED DEVICE REMAPPING AND REPAIR 有权
标题翻译：堆叠设备重新修复和维修
公开(公告)号：US20130003473A1
公开(公告)日：2013-01-03
申请号：US13616704
申请日：2012-09-14
申请人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
发明人： Brent Keeth , Chris G. Martin , Troy A. Manning , Joe M. Jeddeloh , Timothy B. Cowles , Jim Rehmeyer , Paul A. LaBerge
IPC分类号： G11C7/10
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
摘要翻译：各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。描述其他实施例。

5. 发明授权

US08032804B2 Systems and methods for monitoring a memory system 有权
标题翻译：用于监视存储系统的系统和方法
公开(公告)号：US08032804B2
公开(公告)日：2011-10-04
申请号：US12352381
申请日：2009-01-12
申请人： Joe M. Jeddeloh
发明人： Joe M. Jeddeloh
IPC分类号： G11C29/00 , G06F11/00 , G06F12/06 , H01L21/00 , H01L23/02 , H03K5/19
CPC分类号： G06F11/073 , G06F11/0754 , G06F11/0766 , G06F11/3034 , G06F11/3037 , G06F11/3058 , G06F11/3062 , G06F11/3433 , G06F11/3452 , G06F11/3471 , Y02D10/34
摘要： Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.
摘要翻译：本文公开了系统和方法，包括操作以监视与存储器库相关联的第一组操作参数的系统和方法，以调整与存储器保管库相关联的第二组操作参数，以及对主机设备执行警报和报告操作。

6. 发明授权

US08018752B2 Configurable bandwidth memory devices and methods 有权
标题翻译：可配置的带宽内存设备和方法
公开(公告)号：US08018752B2
公开(公告)日：2011-09-13
申请号：US12408906
申请日：2009-03-23
申请人： Joe M. Jeddeloh
发明人： Joe M. Jeddeloh
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G06F13/4234 , G11C5/063 , G11C11/4093 , Y02D10/14 , Y02D10/151
摘要： Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
摘要翻译：描述了存储器件和方法，例如包括一堆存储器管芯和附接的逻辑管芯的存储器件和方法。所描述的方法和设备提供用于为存储器管芯堆栈的选定部分配置带宽。公开了附加设备，系统和方法。

7. 发明申请

US20110194369A1 VARIABLE MEMORY REFRESH DEVICES AND METHODS 有权
标题翻译：可变存储器刷新器件和方法
公开(公告)号：US20110194369A1
公开(公告)日：2011-08-11
申请号：US13088821
申请日：2011-04-18
申请人： Joe M. Jeddeloh
发明人： Joe M. Jeddeloh
IPC分类号： G11C11/402
CPC分类号： G11C11/406 , G11C11/40626 , G11C11/4097 , G11C29/70 , G11C2211/4061
摘要： Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples of different portions include tiles, or arrays, or dies. One memory device and method described includes monitoring and adjusting characteristics of different portions of a 3D stack of memory dies. One characteristic that can be adjusted at multiple selected portions includes refresh rate.
摘要翻译：描述存储器件和方法，例如监视和调整给定存储器件的各种不同部分的特性的存储器件和方法。不同部分的示例包括瓦片，阵列或模具。所描述的一种存储器件和方法包括监测和调整存储器管芯的3D堆叠的不同部分的特性。可以在多个选定部分调整的一个特征包括刷新率。

8. 发明授权

US07978721B2 Multi-serial interface stacked-die memory architecture 有权
标题翻译：多串行接口堆叠存储器架构
公开(公告)号：US07978721B2
公开(公告)日：2011-07-12
申请号：US12261942
申请日：2008-10-30
申请人： Joe M. Jeddeloh , Paul A. LaBerge
发明人： Joe M. Jeddeloh , Paul A. LaBerge
IPC分类号： H04L12/28 , H04J3/00 , G06F13/00 , G06F13/28 , G11C11/00
CPC分类号： G06F13/1668 , G06F13/1684 , G06F13/4022 , G06F2213/16 , Y02D10/14 , Y02D10/151
摘要： Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.
摘要翻译：本文公开的系统和方法基本上同时传送跨越一个或多个发起设备或诸如处理器和交换机的目的地设备之间的对应多个串行化通信链路接口（SCLI）的多个命令，地址和/或数据流。在交换机上，可以将与每个流相对应的一个或多个命令，地址或数据传送到与对应的存储器保险库相关联的对应的目的地存储器保管库控制器（MVC）。目的地MVC可以独立于与耦合到对应的多个存储器库的其他MVC相关联的并行操作执行写入操作，读取操作和/或存储器保管库内务处理操作。

9. 发明申请

US20110167319A1 ERROR CORRECTION IN A STACKED MEMORY 有权
标题翻译：堆叠存储器中的错误校正
公开(公告)号：US20110167319A1
公开(公告)日：2011-07-07
申请号：US12651910
申请日：2010-01-04
申请人： Joe M. Jeddeloh
发明人： Joe M. Jeddeloh
IPC分类号： H03M13/03 , G06F11/10
CPC分类号： H03M13/03 , G06F11/1044 , G06F11/108 , G06F11/1092 , G06F2211/1088
摘要： Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a stack of memory dies with user data and/or first level error correction data stored in a stripe across the memory dies. One such stack can include a second level error correction vault, such as a parity vault, to store parity data corresponding to the user data and/or first level error correction data. Additional apparatus, systems, and methods are disclosed.
摘要翻译：用于构建和操作电子设备和/或系统的电子设备，系统和方法包括具有存储在存储器管芯上的条带中的用户数据和/或第一级错误校正数据的存储器管芯堆叠。一个这样的堆栈可以包括第二级错误校正保险库，例如奇偶校验库，以存储对应于用户数据和/或第一级错误校正数据的奇偶校验数据。公开了附加装置，系统和方法。

10. 发明申请

US20100238693A1 CONFIGURABLE BANDWIDTH MEMORY DEVICES AND METHODS 有权
标题翻译：可配置带宽存储器件和方法
公开(公告)号：US20100238693A1
公开(公告)日：2010-09-23
申请号：US12408906
申请日：2009-03-23
申请人： Joe M. Jeddeloh
发明人： Joe M. Jeddeloh
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/02 , G06F13/4234 , G11C5/063 , G11C11/4093 , Y02D10/14 , Y02D10/151
摘要： Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.
摘要翻译：描述了存储器件和方法，例如包括一堆存储器管芯和附接的逻辑管芯的存储器件和方法。所描述的方法和设备提供用于为存储器管芯堆栈的选定部分配置带宽。公开了附加设备，系统和方法。

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