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1. 发明授权

US08407075B2 Merging calendar entries 失效
标题翻译：合并日历条目
公开(公告)号：US08407075B2
公开(公告)日：2013-03-26
申请号：US12823417
申请日：2010-06-25
申请人： John M. Lance , David B. Cohen , Bruce A. Kahn , Gregory R. Klouda , Ram Krishnamurthy , Deborah E. Maurer , Frank A. Pavelski , Michelle Stoner
发明人： John M. Lance , David B. Cohen , Bruce A. Kahn , Gregory R. Klouda , Ram Krishnamurthy , Deborah E. Maurer , Frank A. Pavelski , Michelle Stoner
IPC分类号： G06Q10/00
CPC分类号： G06F3/0482 , G06Q10/109
摘要： A method, operable on a processing device, for merging calendar entries may include receiving a plurality of calendar entries each associated with entry identification data. The method may also include comparing by the processing device at least a portion of the entry identification data associated with each of the calendar entries. The method may additionally include merging, by the processing device, the calendar entries based at least in part on comparing of at least the portion of the entry identification data associated with each of the at least two calendar entries. The method may further include comparing at least one time attribute associated with each of the calendar entries and comparing at least one textual attribute associated with each of the calendar entries and basing merging the calendar entries additionally on comparing the time attributes and the textual attributes.
摘要翻译：可在处理装置上操作用于合并日历条目的方法可以包括接收与条目标识数据相关联的多个日历条目。该方法还可以包括通过处理设备比较与每个日历条目相关联的条目标识数据的至少一部分。该方法可以另外包括至少部分地基于与至少两个日历条目中的每一个相关联的条目标识数据的至少一部分的比较来由处理设备合并日历条目。该方法还可以包括比较与每个日历条目相关联的至少一个时间属性，并比较与每个日历条目相关联的至少一个文本属性，并且在比较时间属性和文本属性的基础上逐步合并日历条目。

2. 发明申请

US20100070894A1 FEDERATED CALENDAR ENTRY PRESENCE INDICATOR 审中-公开
标题翻译：联合日历录入指示
公开(公告)号：US20100070894A1
公开(公告)日：2010-03-18
申请号：US12211401
申请日：2008-09-16
申请人： Ram Krishnamurthy , John M. Lance , Frank A. Pavelski
发明人： Ram Krishnamurthy , John M. Lance , Frank A. Pavelski
IPC分类号： G06F3/048
CPC分类号： G06F3/0481
摘要： A method for indicating the presence of federated calendar entries in a currently viewed time period of a calendar and/or scheduling application, includes: receiving a user's selection for a date range in a calendar and/or scheduling application; determining whether there are one or more federated calendars associated with the user's calendar and/or scheduling application; wherein in the event there are one or more federated calendars associated with the user's calendar and/or scheduling application: determining whether there are one or more events from the one or more federated calendars in the selected date range; and wherein in the event there are federated calendar events in the selected date range: generating a calendar and/or scheduling page with one or more indicators for federated calendars with events in the selected date range.
摘要翻译：一种用于指示在日历和/或调度应用的当前观看时间段中存在联合日历条目的方法，包括：在日历和/或调度应用中接收用户对日期范围的选择; 确定是否存在与用户的日历和/或调度应用相关联的一个或多个联合日历; 其中在所述事件中存在与所述用户日历和/或调度应用程序相关联的一个或多个联合日历：确定在所选择的日期范围内是否存在来自所述一个或多个联合日历的一个或多个事件; 并且其中在所述选择的日期范围内存在联合日历事件的情况下：在具有所选日期范围内的事件的联合日历中生成具有一个或多个指示符的日历和/或调度页面。

3. 发明授权

US10825509B2 Full-rail digital read compute-in-memory circuit 有权
公开(公告)号：US10825509B2
公开(公告)日：2020-11-03
申请号：US16146932
申请日：2018-09-28
申请人： Huseyin Ekin Sumbul , Gregory K. Chen , Raghavan Kumar , Phil Knag , Abhishek Sharma , Sasikanth Manipatruni , Amrita Mathuriya , Ram Krishnamurthy , Ian A. Young
发明人： Huseyin Ekin Sumbul , Gregory K. Chen , Raghavan Kumar , Phil Knag , Abhishek Sharma , Sasikanth Manipatruni , Amrita Mathuriya , Ram Krishnamurthy , Ian A. Young
IPC分类号： G11C11/00 , G11C11/419 , G11C27/02 , G11C7/10 , G11C7/12 , G11C11/412 , G11C11/418
摘要： A full-rail digital-read CIM circuit enables a weighted read operation on a single row of a memory array. A weighted read operation captures a value of a weight stored in the single memory array row without having to rely on weighted row-access. Rather, using full-rail access and a weighted sampling capacitance network, the CIM circuit enables the weighted read operation even under process variation, noise and mismatch.

4. 发明申请

US20190057050A1 PIPELINE CIRCUIT ARCHITECTURE TO PROVIDE IN-MEMORY COMPUTATION FUNCTIONALITY 审中-公开
公开(公告)号：US20190057050A1
公开(公告)日：2019-02-21
申请号：US16160952
申请日：2018-10-15
申请人： Amrita Mathuriya , Sasikanth Manipatruni , Victor W. Lee , Abhishek Sharma , Huseyin E. Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , Ian Young
发明人： Amrita Mathuriya , Sasikanth Manipatruni , Victor W. Lee , Abhishek Sharma , Huseyin E. Sumbul , Gregory Chen , Raghavan Kumar , Phil Knag , Ram Krishnamurthy , Ian Young
IPC分类号： G06F13/16 , G06F13/28
摘要： Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

5. 发明申请

US20070299902A1 Sparse tree adder 审中-公开
标题翻译：稀疏树加法器
公开(公告)号：US20070299902A1
公开(公告)日：2007-12-27
申请号：US11475704
申请日：2006-06-26
申请人： Mahesh K. Kumashikar , Sanu Mathew , Ram Krishnamurthy , Daniel Jackson
发明人： Mahesh K. Kumashikar , Sanu Mathew , Ram Krishnamurthy , Daniel Jackson
IPC分类号： G06F7/52
CPC分类号： G06F7/508
摘要： Embodiments disclosed herein provide sparse adder circuits comprising Ling type propagate and generate circuits and sparse carry circuits to efficiently add first and second operands to one another.
摘要翻译：本文公开的实施例提供稀疏加法器电路，其包括Ling型传播并产生电路和稀疏传送电路以有效地将第一和第二操作数彼此添加。

6. 发明申请

US20070233772A1 Modular multiplication acceleration circuit and method for data encryption/decryption 失效
标题翻译：模块化乘法加速电路和数据加密/解密方法
公开(公告)号：US20070233772A1
公开(公告)日：2007-10-04
申请号：US11393392
申请日：2006-03-30
申请人： Sanu Mathew , Ram Krishnamurthy , Zheng Guo
发明人： Sanu Mathew , Ram Krishnamurthy , Zheng Guo
IPC分类号： G06F7/52
CPC分类号： G06F7/728 , G06F7/722
摘要： A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1, addition of a least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1, multiplication of the least-significant bit of X and bits 2w-1:w of Y to generate bits 2w-1:w of product Z, and addition of bits 2w-1:w of modulus M to bits 2w-1:w of product Z if the least-significant bit of product Z is 1. Multiplying the least-significant bit of X and bits 2w-1:w of Y may occur at least partially contemporaneously with multiplying the least-significant bit of X and the least-significant w bits of Y, determining if the least-significant bit of product Z is 1, and adding the least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1.
摘要翻译：处理乘法器X和被乘数Y的系统可以包括X的最低有效位和Y的最低有效位W的乘法以产生乘积Z的最低有效w位。系统还可以包括确定是否如果产品Z的最低有效位为1，乘积Z的最低有效位为1，则将乘积Z的最低有效位加上最低有效W位的模M，并且产生Z的位2 w-1：w，并将模数M的位2 w-1：w相加到乘积Z的位2 w-1：w，如果乘积Z的最低有效位为1.乘以X的最低有效位和Y的位2 w-1：w可以至少部分同时与X的最低有效位乘以最小有效位W 确定产品Z的最低有效位是否为1，并将模数M的最低有效W位加到第如果产品Z的最低有效位为1，则产品Z的最低有效w位。

7. 发明授权

US07250783B2 Current mirror multi-channel leakage current monitor circuit and method 有权
标题翻译：电流镜多通道漏电流监测电路及方法
公开(公告)号：US07250783B2
公开(公告)日：2007-07-31
申请号：US11022800
申请日：2004-12-28
申请人： Steven K. Hsu , Ram Krishnamurthy , Chris Hyung-il Kim
发明人： Steven K. Hsu , Ram Krishnamurthy , Chris Hyung-il Kim
IPC分类号： G01R31/02
CPC分类号： G11C29/50 , G01R31/3012 , G11C2029/5004 , G11C2029/5006
摘要： A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.
摘要翻译：电流镜多通道泄漏监控电路和方法测量管芯泄漏，并产生数字保持器控制位以控制过程补偿动态电路。泄漏监测器可在芯片上的多个位置进行高分辨率片上泄漏测量，从而节省测试时间，并使裸片和裸片工艺补偿均可实现。

8. 发明授权

US07154300B2 Encoder and decoder circuits for dynamic bus 有权
标题翻译：用于动态总线的编码器和解码器电路
公开(公告)号：US07154300B2
公开(公告)日：2006-12-26
申请号：US10744084
申请日：2003-12-24
申请人： Mark A. Anders , Himanshu Kaul , Ram Krishnamurthy
发明人： Mark A. Anders , Himanshu Kaul , Ram Krishnamurthy
IPC分类号： H03K19/0175 , G06F13/00 , G11C7/00
CPC分类号： H04L25/0278 , H04L25/028
摘要： A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.
摘要翻译：提供动态总线架构。这可以包括耦合到总线线路的编码电路和耦合到总线线路的解码器电路。编码器电路可以接收输入信号并在总线上生成编码信号。解码器电路可以从总线接收编码信号并产生原始未编码信号。编码器电路可以包括第一触发器电路，其基于来自总线的时钟信号来存储来自总线的先前输入信号。此外，解码器电路可以包括具有时钟输入的第二触发器电路，以从总线接收编码信号作为时钟输入。

9. 发明授权

US07131055B2 Fast bit-parallel Viterbi decoder add-compare-select circuit 失效
标题翻译：快速位并行维特比解码器加比较选择电路
公开(公告)号：US07131055B2
公开(公告)日：2006-10-31
申请号：US10372121
申请日：2003-02-25
申请人： Sanu K. Mathew , Ram Krishnamurthy , Hoang Q. Dao
发明人： Sanu K. Mathew , Ram Krishnamurthy , Hoang Q. Dao
IPC分类号： H03M13/03
CPC分类号： H03M13/6502 , H03M13/4107
摘要： A Viterbi decoder includes an ACS unit that performs state metric updates for every symbol cycle. State metric updates involve adding the state metrics corresponding to a likely input symbol to the respective branch matrix, comparing the results of the additions to determine which is smaller, and selecting the smaller result for the next state metric. The ACS unit includes two parallel adders followed by a parallel comparator that generates a multiplexer-select signal. The outputs of the parallel adders are input into a multiplexer and the multiplexer-select signal is input into the multiplexer for a decision.
摘要翻译：维特比解码器包括对每个符号周期执行状态度量更新的ACS单元。状态度量更新涉及将对应于可能的输入符号的状态量度相加到相应的分支矩阵，比较添加的结果以确定哪个更小，并为下一状态度量选择较小的结果。 ACS单元包括两个并行加法器，其后是并行比较器，其产生多路选择器选择信号。并行加法器的输出被输入到多路复用器中，并且多路复用器选择信号被输入到多路复用器中用于决定。

10. 发明授权

US07016239B2 Leakage tolerant register file 失效
标题翻译：漏电容量寄存器文件
公开(公告)号：US07016239B2
公开(公告)日：2006-03-21
申请号：US10676985
申请日：2003-09-30
申请人： Bhaskar P. Chatterjee , Steven K. Hsu , Sriram R. Vangal , Ram Krishnamurthy
发明人： Bhaskar P. Chatterjee , Steven K. Hsu , Sriram R. Vangal , Ram Krishnamurthy
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C8/10
摘要： A register file contains a local bit trace and a driving signal trace as well as a plurality of data cells coupled to the local bit trace. A device is coupled to the driving signal trace and the local bit trace to intelligently charge and float the local bit trace. The intelligent charging and floating is facilitated by determination of a selection of one of the data cells.
摘要翻译：寄存器文件包含本地位跟踪和驱动信号跟踪以及耦合到本地位跟踪的多个数据单元。一个器件耦合到驱动信号跟踪和本地位跟踪，以智能地对本地位跟踪进行充电和浮动。通过确定数据单元之一的选择来促进智能充电和浮动。

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