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1. 发明授权

US07813186B2 Flash memory device and programming method thereof 有权
标题翻译：闪存设备及其编程方法
公开(公告)号：US07813186B2
公开(公告)日：2010-10-12
申请号：US12130955
申请日：2008-05-30
申请人： Seong Hun Park , Jong Hyun Wang
发明人： Seong Hun Park , Jong Hyun Wang
IPC分类号： G11C7/10
CPC分类号： G06F11/1068 , G11C16/3454 , G11C2216/14
摘要： A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data line and configured to receive verification data through a page buffer during a verify operation. The flash memory device also includes a fail bit counter unit for counting the verification data, comparing counted fail bits and the number of ECC allowed bits, and outputting a pass or fail signal of a program operation according to the comparison result.
摘要翻译：一种闪速存储装置，包括：包括多个存储单元的存储单元阵列，包括与存储单元阵列的位线连接的多个页缓冲器的页缓冲器单元，连接在页缓冲器单元和数据之间的数据线复用单元并配置为在验证操作期间通过页面缓冲区接收验证数据。闪存装置还包括用于对验证数据进行计数的故障位计数器单元，比较计数故障位和ECC允许位数，并根据比较结果输出程序运行的通过或失败信号。

2. 发明授权

US07751241B2 Read method of memory device 有权
标题翻译：读存储器件的方法
公开(公告)号：US07751241B2
公开(公告)日：2010-07-06
申请号：US12422870
申请日：2009-04-13
申请人： Jong Hyun Wang , Jun Seop Chung , Seok Jin Joo
发明人： Jong Hyun Wang , Jun Seop Chung , Seok Jin Joo
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G06F11/1072 , G11C11/5642 , G11C29/00
摘要： A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a Nth (N≧3, N is an integer) read command.
摘要翻译：包括MLC的存储器件的读取方法包括以下步骤：根据第一读取命令执行数据读取操作; 确定读取数据的纠错是否可行; 如果作为确定的结果，难以进行纠错，则根据第二读取命令执行数据读取操作; 根据第二读取命令确定读取数据的纠错是否可行; 如果作为确定的结果，难以进行纠错，则根据第N（N≥3，N是整数）读取命令执行数据读取操作。

3. 发明申请

US20090161444A1 PAGE BUFFER AND PROGRAMMING METHOD OF A NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件的页面缓冲器和编程方法
公开(公告)号：US20090161444A1
公开(公告)日：2009-06-25
申请号：US12130981
申请日：2008-05-30
申请人： Se Chun Park , Jong Hyun Wang , Yu Jong Noh
发明人： Se Chun Park , Jong Hyun Wang , Yu Jong Noh
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/10 , G11C2216/14
摘要： A page buffer includes a first ground voltage supply unit for applying a ground voltage to first and second registers according to a level of a sense node, and a second ground voltage supply unit for applying the ground voltage to the first and second registers irrespective of a level of the sense node. A method of programming a non-volatile memory device includes storing a high-level data in a first node of a first register of a plurality of page buffers, precharging a sense node with a high level, resetting the data stored in the first node of the first register according to a voltage level of the sense node, precharging the sense node with a high level, storing external data in the first node according to a voltage level of the sense node, and performing a program operation according to the data stored in the first node.
摘要翻译：页面缓冲器包括用于根据感测节点的电平将接地电压施加到第一和第二寄存器的第一接地电压供应单元和用于将接地电压施加到第一和第二寄存器的第二接地电压供应单元，而不管感知节点的级别。一种编程非易失性存储器件的方法包括将高电平数据存储在多个页缓冲器的第一寄存器的第一节点中，对具有高电平的感测节点进行预充电，将存储在第一节点中的数据重置所述第一寄存器根据所述感测节点的电压电平，对所述感测节点进行高电平预充电，根据所述感测节点的电压电平将外部数据存储在所述第一节点中，并且根据存储在所述感测节点中的数据进行编程操作第一个节点。

4. 发明申请

US20090141560A1 FLASH MEMORY DEVICE AND PROGRAMMING METHOD THEREOF 有权
标题翻译：闪存存储器件及其编程方法
公开(公告)号：US20090141560A1
公开(公告)日：2009-06-04
申请号：US12130955
申请日：2008-05-30
申请人： Seong Hun PARK , Jong Hyun Wang
发明人： Seong Hun PARK , Jong Hyun Wang
IPC分类号： G11C16/06
CPC分类号： G06F11/1068 , G11C16/3454 , G11C2216/14
摘要： A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data line and configured to receive verification data through a page buffer during a verify operation. The flash memory device also includes a fail bit counter unit for counting the verification data, comparing counted fail bits and the number of ECC allowed bits, and outputting a pass or fail signal of a program operation according to the comparison result.
摘要翻译：一种闪速存储装置，包括：包括多个存储单元的存储单元阵列，包括与存储单元阵列的位线连接的多个页缓冲器的页缓冲器单元，连接在页缓冲器单元和数据之间的数据线复用单元并配置为在验证操作期间通过页面缓冲区接收验证数据。闪存装置还包括用于对验证数据进行计数的故障位计数器单元，比较计数故障位和ECC允许位数，并根据比较结果输出程序运行的通过或失败信号。

5. 发明申请

US20090097313A1 PAGE BUFFER, MEMORY DEVICE HAVING THE PAGE BUFFER AND METHOD OF OPERATING THE SAME 失效
标题翻译：页面缓冲区，具有页面缓冲区的存储器件及其操作方法
公开(公告)号：US20090097313A1
公开(公告)日：2009-04-16
申请号：US12019938
申请日：2008-01-25
申请人： Se Chun PARK , Jong Hyun Wang
发明人： Se Chun PARK , Jong Hyun Wang
IPC分类号： G11C16/10 , G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C2211/5621 , G11C2211/5622 , G11C2216/14
摘要： A page buffer includes a first latch coupled between a sensing node and a data input/output node for storing data to be programmed. The sensing node is coupled to a bit line corresponding to an MLC selected for programming. The data input/output node receives/outputs data. A second latch is coupled to the sensing node for performing a program, verifying or read operation. A first switching means is coupled between the first latch and the sensing node for transmitting data stored in the first latch to the bit line through the sensing node when the program operation is performed. A second switching means is coupled to a first node of the second latch and the sensing node for verifying a first program operation. A third switching means is coupled between a second node of the second latch and the sensing node for verifying a second program operation.
摘要翻译：页面缓冲器包括耦合在感测节点和用于存储要编程的数据的数据输入/输出节点之间的第一锁存器。感测节点耦合到对应于选择用于编程的MLC的位线。数据输入/输出节点接收/输出数据。第二锁存器耦合到感测节点，用于执行程序，验证或读取操作。当执行编程操作时，第一开关装置耦合在第一锁存器和感测节点之间，用于将存储在第一锁存器中的数据传送到通过感测节点的位线。第二切换装置耦合到第二锁存器的第一节点和用于验证第一程序操作的感测节点。第三开关装置耦合在第二锁存器的第二节点和用于验证第二编程操作的感测节点之间。

6. 发明授权

US08000154B2 Non-volatile memory device and method of controlling a bulk voltage thereof 失效
标题翻译：非易失性存储器件及其体电压的控制方法
公开(公告)号：US08000154B2
公开(公告)日：2011-08-16
申请号：US12130931
申请日：2008-05-30
申请人： Chae Kyu Jang , Jong Hyun Wang , Suk Yun , Seong Hun Park
发明人： Chae Kyu Jang , Jong Hyun Wang , Suk Yun , Seong Hun Park
IPC分类号： G11C5/14
CPC分类号： G11C16/10 , G11C16/349
摘要： A non-volatile memory device comprises a voltage supplier comprising memory cells in which the voltage supplier supplies a positive set voltage to a bulk of a memory cell array at the time of a read operation of the memory cells and a controller for controlling the voltage supplier to set and supply a bulk voltage depending on a number of erase/program cycles of the memory cell array.
摘要翻译：非易失性存储器件包括电压供应器，其包括存储器单元，其中电压供应器在存储器单元的读取操作时向存储单元阵列的大部分提供正设定电压，以及用于控制电压供应器以根据存储器单元阵列的擦除/编程周期的数量来设置和提供体电压。

7. 发明授权

US07969786B2 Method of programming nonvolatile memory device 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US07969786B2
公开(公告)日：2011-06-28
申请号：US12361231
申请日：2009-01-28
申请人： Jong Hyun Wang
发明人： Jong Hyun Wang
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A method of programming nonvolatile memory devices. A program operation is performed by applying a dummy program pulse having a pulse width wider than a pulse width of a program start pulse. A program operation is performed by applying the program start pulse. It is then verified whether a program has been completed as a result of the program operation. A program operation is performed by applying a step-shaped dummy program pulse, which has a second pulse width and has been increased by a second step voltage. A program operation is performed by applying a program pulse having a first step voltage and a first pulse width. It is then verified whether a program has been completed as a result of the program operation.
摘要翻译：一种编程非易失性存储器件的方法。通过应用具有比程序开始脉冲的脉冲宽度更宽的脉冲宽度的虚拟编程脉冲来执行编程操作。通过应用程序启动脉冲来执行编程操作。然后，由程序运行结果验证程序是否已经完成。通过应用具有第二脉冲宽度并已经增加第二阶梯电压的阶梯形伪程序脉冲来执行编程操作。通过施加具有第一阶跃电压和第一脉冲宽度的编程脉冲来执行编程操作。然后，由程序运行结果验证程序是否已经完成。

8. 发明授权

US07706190B2 Method of program-verifying a nonvolatile memory device using subdivided verifications with increasing verify voltages 失效
标题翻译：使用增加的验证电压的细分验证对非易失性存储器件进行程序验证的方法
公开(公告)号：US07706190B2
公开(公告)日：2010-04-27
申请号：US12163921
申请日：2008-06-27
申请人： Chang Won Yang , Jong Hyun Wang , Se Chun Park
发明人： Chang Won Yang , Jong Hyun Wang , Se Chun Park
IPC分类号： G11C16/34
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/3459 , G11C2211/5621
摘要： In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved.
摘要翻译：在操作非易失性存储器装置的方法中，通过增加验证电压来执行细分验证。因此，存储器单元的阈值电压分布可以变窄，因此可以提高闪速存储器件的程序性能。

9. 发明授权

US07450432B2 Method of programming data in a flash memory device 失效
标题翻译：在闪存设备中编程数据的方法
公开(公告)号：US07450432B2
公开(公告)日：2008-11-11
申请号：US11771792
申请日：2007-06-29
申请人： Jong Hyun Wang
发明人： Jong Hyun Wang
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： A method of programming a most significant bit (MSB) data to a multi-level cell in a flash memory device including first and second cells includes performing a first program operation on the first cell using a first program voltage, the first cell being in a first state when the first program operation is performed on the first cell; if the first cell is determined to be in a second state after the first program operation, defining a second program voltage based on a result of comparing the first program voltage with a start voltage predefined for a second program operation; and performing the second program operation on the second cell using the second program voltage that has been defined according to a result of the comparison between the first program voltage and the start voltage.
摘要翻译：一种将最高有效位（MSB）数据编程到包括第一和第二单元的闪存器件中的多电平单元的方法包括使用第一编程电压对第一单元执行第一编程操作，第一单元位于当在第一单元上执行第一编程操作时的第一状态; 如果在第一编程操作之后确定第一单元处于第二状态，则基于将第一编程电压与为第二编程操作预定的启动电压进行比较的结果来定义第二编程电压; 以及使用根据第一编程电压和起始电压之间的比较结果定义的第二编程电压对第二单元执行第二编程操作。

10. 发明申请

US20080205138A1 MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：存储器件及其操作方法
公开(公告)号：US20080205138A1
公开(公告)日：2008-08-28
申请号：US11966007
申请日：2007-12-28
申请人： Jong Hyun Wang , Duck Ju Kim , Seong Hun Park , Chang Won Yang
发明人： Jong Hyun Wang , Duck Ju Kim , Seong Hun Park , Chang Won Yang
IPC分类号： G11C16/06 , G11C7/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array.
摘要翻译：存储器件具有多层单元（MLC）的存储单元。存储单元阵列包括多个单元串，每个串提供在位线和公共源极线之间，其中在编程验证时将正电压施加到公共源极线。页面缓冲器被配置为对MLC进行编程，读取存储器单元并执行程序验证。通过顺序地增加位线选择信号的电压电平直到位线选择信号达到足以验证存储单元阵列中选定单元的编程状态的电压来执行该程序验证。

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