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1. 发明授权

US08810268B2 Built-in self-test circuit for liquid crystal display source driver 有权
标题翻译：内置自检电路，用于液晶显示源驱动
公开(公告)号：US08810268B2
公开(公告)日：2014-08-19
申请号：US12764346
申请日：2010-04-21
申请人： Jui-Cheng Huang , Yung-Chow Peng , Ruey-Bin Sheen
发明人： Jui-Cheng Huang , Yung-Chow Peng , Ruey-Bin Sheen
IPC分类号： G01R31/3187
CPC分类号： G09G3/3685 , G09G3/006 , G09G2310/027 , G09G2310/0291 , G09G2330/12
摘要： A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range.
摘要翻译：用于液晶显示器（LCD）源驱动器的内置自检（BIST）电路包括至少一个数模转换器（DAC）和耦合到相应DAC的至少一个缓冲器，其中缓冲器可重新配置作为比较。第一输入信号和第二输入信号耦合到比较器。第一输入信号是预定的参考电压电平。第二输入信号是测试范围内的测试偏移电压。

2. 发明授权

US09287252B2 Semiconductor mismatch reduction 有权
标题翻译：半导体失配减少
公开(公告)号：US09287252B2
公开(公告)日：2016-03-15
申请号：US13048411
申请日：2011-03-15
申请人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
发明人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
IPC分类号： H01L29/12 , H01L27/02
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译：公开了一种用于减小密度失配的系统和方法。一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

3. 发明申请

US20120235208A1 Semiconductor Mismatch Reduction 有权
标题翻译：半导体失配减少
公开(公告)号：US20120235208A1
公开(公告)日：2012-09-20
申请号：US13048411
申请日：2011-03-15
申请人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
发明人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
IPC分类号： H01L29/12 , H01L21/66
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译：公开了一种用于减小密度失配的系统和方法。一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

4. 发明授权

US08363772B2 Methods for eliminating phase distortion in signals 有权
标题翻译：消除信号相位失真的方法
公开(公告)号：US08363772B2
公开(公告)日：2013-01-29
申请号：US11807521
申请日：2007-05-29
申请人： Ruey-Bin Sheen
发明人： Ruey-Bin Sheen
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03K5/1534 , H03K5/26
摘要： A circuit for reducing phase distortion of a first signal and a second signal is provided, wherein the first and the second signals are complementary. The circuit includes a detecting circuit for detecting a first edge of the first signal and a second edge of the second signal, wherein the second edge immediately follows the first edge and is in a same direction as the first edge; an output node; and a signal regenerator connected to the detecting circuit and the output node. The signal regenerator is configured to generate an output signal having an additional first edge and an additional second edge. The additional first edge and the additional second edge are opposite edges substantially aligned to the first edge and the second edge, respectively. The additional first edge and the additional second edge are immediate neighboring edges.
摘要翻译：提供了用于减少第一信号和第二信号的相位失真的电路，其中第一和第二信号是互补的。该电路包括用于检测第一信号的第一边缘和第二信号的第二边缘的检测电路，其中第二边缘紧接着第一边缘并且处于与第一边缘相同的方向; 输出节点; 以及连接到检测电路和输出节点的信号再生器。信号再生器被配置为产生具有附加的第一边缘和附加的第二边缘的输出信号。附加的第一边缘和附加的第二边缘分别相对于第一边缘和第二边缘大致对准的相对边缘。附加的第一边缘和附加的第二边缘是紧邻的边缘。

5. 发明申请

US20080297200A1 Methods for eliminating phase distortion in signals 有权
标题翻译：消除信号相位失真的方法
公开(公告)号：US20080297200A1
公开(公告)日：2008-12-04
申请号：US11807521
申请日：2007-05-29
申请人： Ruey-Bin Sheen
发明人： Ruey-Bin Sheen
IPC分类号： G01R25/00
CPC分类号： H03K5/1534 , H03K5/26
摘要： A circuit for reducing phase distortion of a first signal and a second signal is provided, wherein the first and the second signals are complementary. The circuit includes a detecting circuit for detecting a first edge of the first signal and a second edge of the second signal, wherein the second edge immediately follows the first edge and is in a same direction as the first edge; an output node; and a signal regenerator connected to the detecting circuit and the output node. The signal regenerator is configured to generate an output signal having an additional first edge and an additional second edge. The additional first edge and the additional second edge are opposite edges substantially aligned to the first edge and the second edge, respectively. The additional first edge and the additional second edge are immediate neighboring edges.
摘要翻译：提供了用于减少第一信号和第二信号的相位失真的电路，其中第一和第二信号是互补的。该电路包括用于检测第一信号的第一边缘和第二信号的第二边缘的检测电路，其中第二边缘紧接着第一边缘并且处于与第一边缘相同的方向; 输出节点; 以及连接到检测电路和输出节点的信号再生器。信号再生器被配置为产生具有附加的第一边缘和附加的第二边缘的输出信号。附加的第一边缘和附加的第二边缘分别相对于第一边缘和第二边缘大致对准的相对边缘。附加的第一边缘和附加的第二边缘是紧邻的边缘。

6. 发明授权

US07268712B1 System and method for calibrating on-die components 有权
标题翻译：用于校准模内部件的系统和方法
公开(公告)号：US07268712B1
公开(公告)日：2007-09-11
申请号：US11406947
申请日：2006-04-18
申请人： Ruey-Bin Sheen
发明人： Ruey-Bin Sheen
IPC分类号： H03M1/10
CPC分类号： H04L25/0278
摘要： An on-die calibration system includes an external reference component, a first and a second on-die adjustable components, and a calibration module coupled to the reference component, the first and second components, wherein the calibration module calibrates the first component according to the reference component and calibrates the second component according to the calibrated first component.
摘要翻译：片上校准系统包括外部参考部件，第一和第二管芯上可调节部件以及耦合到参考部件第一和第二部件的校准模块，其中校准模块根据第一和第二部件校准第一部件参考组件，并根据校准的第一组件校准第二组件。

7. 发明授权

US09363115B2 System and method for aligning data bits 有权
标题翻译：用于对齐数据位的系统和方法
公开(公告)号：US09363115B2
公开(公告)日：2016-06-07
申请号：US13539519
申请日：2012-07-02
申请人： Ying-Yu Hsu , Ruey-Bin Sheen , Shih-Hung Lan , Chih-Hsien Chang
发明人： Ying-Yu Hsu , Ruey-Bin Sheen , Shih-Hung Lan , Chih-Hsien Chang
IPC分类号： G06F11/07 , H04L25/14 , G06F13/16
CPC分类号： H04L25/14 , G06F13/1689
摘要： Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.
摘要翻译：公开了通过调整这些数据位的输入线的定时来对准多个数据位的系统和方法。实施例包括用于比较多组位的定时的分层结构。其他实施例包括在3D管芯堆叠架构中对准来自多个芯片的数据位。

8. 发明申请

US20130187677A1 SYSTEM AND METHOD FOR CALIBRATING CHIPS IN A 3D CHIP STACK ARCHITECTURE 有权
公开(公告)号：US20130187677A1
公开(公告)日：2013-07-25
申请号：US13355024
申请日：2012-01-20
申请人： Ying-Yu Hsu , Ruey-Bin Sheen , Chih-Hsien Chang
发明人： Ying-Yu Hsu , Ruey-Bin Sheen , Chih-Hsien Chang
IPC分类号： G01R31/26
CPC分类号： H03K3/012 , G01R31/26 , G01R31/2607 , G01R31/3004 , G01R31/3191 , G01R31/31924 , G01R31/3193 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2225/06596 , H01L2924/0002 , H03K3/017 , H03K17/94 , H01L2924/00
摘要： A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.

9. 发明授权

US08866508B2 System and method for calibrating chips in a 3D chip stack architecture 有权
标题翻译：用于在3D芯片堆栈架构中校准芯片的系统和方法
公开(公告)号：US08866508B2
公开(公告)日：2014-10-21
申请号：US13355024
申请日：2012-01-20
申请人： Ying-Yu Hsu , Ruey-Bin Sheen , Chih-Hsien Chang
发明人： Ying-Yu Hsu , Ruey-Bin Sheen , Chih-Hsien Chang
IPC分类号： G01R31/02 , G01R31/30 , G01R31/26 , G01R31/319 , G01R31/3193
CPC分类号： H03K3/012 , G01R31/26 , G01R31/2607 , G01R31/3004 , G01R31/3191 , G01R31/31924 , G01R31/3193 , H01L25/0657 , H01L25/18 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2225/06596 , H01L2924/0002 , H03K3/017 , H03K17/94 , H01L2924/00
摘要： A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.
摘要翻译：公开了用于自适应地调整3D架构/堆叠中的第一和第二芯片之间的信号的驱动强度的系统和方法。这可以用于在3D架构/堆栈中自适应地校准芯片。该系统可以包括一个芯片上的传输电路和另一芯片上的接收器电路。或者，系统可以仅在一个芯片上包括发送和接收电路。

10. 发明申请

US20060039513A1 Clock and data recovery systems and methods 审中-公开
标题翻译：时钟和数据恢复系统和方法
公开(公告)号：US20060039513A1
公开(公告)日：2006-02-23
申请号：US10919429
申请日：2004-08-17
申请人： Ruey-Bin Sheen , Chih-Hsien Chang
发明人： Ruey-Bin Sheen , Chih-Hsien Chang
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： Methods of clock and data recovery (CDR) are provided. An exemplary method comprises extending the eye of the data stream by examining transitions of adjacent samples, detecting whether an island sample exists in each symbol according to the separation of the transitions, and altering the value of the neighboring samples near the island sample to be equal to the island sample.
摘要翻译：提供了时钟和数据恢复（CDR）的方法。一种示例性方法包括通过检查相邻样本的转变来扩展数据流的眼睛，根据转换的间隔检测每个符号中是否存在岛样本，以及将岛样本附近的相邻样本的值改变为相等到岛样品。

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