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1. 发明授权

US09679911B2 Semiconductor memory device and production method thereof 有权
公开(公告)号：US09679911B2
公开(公告)日：2017-06-13
申请号：US14970919
申请日：2015-12-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ryosuke Sawabe , Shigeki Kobayashi , Takamasa Okawa , Kei Sakamoto
IPC分类号： H01L29/76 , H01L27/11582 , H01L21/768 , H01L21/02 , H01L27/11556
CPC分类号： H01L27/11582 , H01L21/02532 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76877 , H01L23/485 , H01L27/11556 , H01L27/1157
摘要： A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween.

2. 发明授权

US08923031B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08923031B2
公开(公告)日：2014-12-30
申请号：US13778849
申请日：2013-02-27
申请人： Kabushiki Kaisha Toshiba
发明人： Kei Sakamoto , Masaki Kondo , Nobuaki Yasutake , Takayuki Okamura
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0002 , G11C13/004 , G11C13/0069 , G11C2213/72
摘要： A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.
摘要翻译：根据实施例的半导体存储器件包括：存储单元阵列，包括多个第一线，多条第二线和设置在第一线和第二线的每个交点处的存储单元; 以及控制电路，被配置为向所选择的第一线施加第一电压，将具有小于第一电压的电压值的第二电压施加到所选择的第二线，并将第三电压和第四电压施加到未选择的第一行和未选择的第二行。控制电路被配置为向与所选择的第一行相邻的未选择的第一行之一施加第五电压，并且将第六电压施加到与所选择的第二行相邻的未选择的第二行之一。

3. 发明授权

US08917538B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08917538B2
公开(公告)日：2014-12-23
申请号：US14086638
申请日：2013-11-21
申请人： Kabushiki Kaisha Toshiba
发明人： Kei Sakamoto
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0097 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C2213/72
摘要： A nonvolatile semiconductor memory device includes a memory cell array including memory cells having a variable resistance element provided at intersections of crossing first and second lines, the memory cell array including third lines, fourth and fifth lines, and first and second diodes; and a control circuit which, when the memory cells include a selected memory cell, a selected first line connected to the selected memory cell and an unselected first line, and a selected second line connected to the selected memory cell and an unselected second line, supplies a first voltage to the selected first line, and supplies a second voltage to the unselected first line, and when the third lines include a selected third line electrically connected to the selected second line via one of the fourth line and a first diode, supplies a third voltage to the selected fourth line.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，其包括存储单元，该存储单元具有设置在交叉的第一和第二线的交点处的可变电阻元件，所述存储单元阵列包括第三线，第四和第五线以及第一和第二二极管; 以及控制电路，当所述存储单元包括所选择的存储单元时，连接到所选择的存储单元的选定的第一行和未选择的第一行，以及连接到所选存储单元和未选择的第二行的所选择的第二行，向所选择的第一线路提供第一电压，并且向未选择的第一线路提供第二电压，并且当第三线路包括经由第四线路和第一二极管之一电连接到所选择的第二线路的选择的第三线路时，第三电压到所选择的第四行。

4. 发明授权

US10945199B2 Vehicle-mounted gateway apparatus and vehicle mounted gateway system 有权
公开(公告)号：US10945199B2
公开(公告)日：2021-03-09
申请号：US16303931
申请日：2017-05-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA DIGITAL SOLUTIONS CORPORATION
发明人： Masayuki Omiya , Kazuhiro Gotou , Masashi Uemoto , Daichi Soshi , Kazunori Hashimoto , Hirokazu Ikeyama , Yousuke Ujihara , Satoru Iwahashi , Akifumi Ohno , Kei Sakamoto , Ken Ishii , Shion Itou
IPC分类号： H04L12/40 , H04W48/18 , H04W4/44 , H04W24/08
摘要： A vehicle-mounted gateway apparatus according to an embodiment includes a communication device including an external communication interface for connection to the network outside the mobile body with each of a plurality of different external communication schemes and an internal communication interface for connection to each of the plurality of data sources within the mobile body; and a control device configured to transmit data collected from each of the data sources through the internal communication interface to the network outside the mobile body. The control device includes a communication channel selection section configured to select a communication channel from the plurality of external communication schemes for each of the data sources, and a monitoring control section configured to monitor data output from each of the data sources and to transmit the data to the network outside the mobile body over a selected one of the communication channels associated with the data source. The communication channel selection section is configured to switch between the communication channels associated with each of the data sources depending on a communication connection state of each of the plurality of external communication schemes based on priority setting in which the plurality of external communication schemes are arranged in a predetermined priority order.

5. 发明授权

US09111858B2 Non-volatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US09111858B2
公开(公告)日：2015-08-18
申请号：US13838722
申请日：2013-03-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Jun Nishimura , Nobuaki Yasutake , Kei Sakamoto , Takayuki Okamura
IPC分类号： H01L21/336 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1641 , H01L45/1675
摘要： A non-volatile semiconductor memory device includes a cell array layer including a first wire, one or more memory cells stacked on the first wire, and a second wire formed on the memory cell so as to cross the first wire, wherein the memory cell includes a current rectifying element and a variable resistance element, and an atomic composition ratio of nitrogen is higher than that of oxygen in a part of a sidewall of the current rectifying element.
摘要翻译：一种非易失性半导体存储器件包括：单元阵列层，包括第一布线，堆叠在第一布线上的一个或多个存储单元，以及形成在存储单元上以跨越第一布线的第二布线，其中存储单元包括电流整流元件和可变电阻元件，并且氮的原子组成比高于当前整流元件的侧壁的一部分中的氧的原子组成比。

6. 发明申请

US20140003127A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140003127A1
公开(公告)日：2014-01-02
申请号：US13778371
申请日：2013-02-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kei Sakamoto , Takayuki Okamura , Nobuaki Yasutake , Jun Nishimura
IPC分类号： G11C13/00
CPC分类号： G11C13/0002 , G11C13/0023 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/12 , H01L45/1233
摘要： A semiconductor memory device according to an embodiment includes a memory cell array including memory cells, the memory cells each configured having a current rectifier element and a variable resistance element connected in series therein. Each of the memory cells has formed on aside surface thereof: a first insulating film provided on aside surface of the current rectifier element and the variable resistance element and having a composition ratio of anon-silicon element to silicon which is a first value; a silicon oxide film provided on a side surface of the first insulating film; and a second insulating film provided on aside surface of the silicon oxide film and having a composition ratio of a non-silicon element to silicon which is a second value. The first value is smaller than the second value.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列，该存储单元阵列包括存储单元，每个存储单元均配置有电流整流元件和串联连接的可变电阻元件。每个存储单元形成在其旁边表面上：设置在电流整流元件和可变电阻元件的另一表面上的第一绝缘膜，并且具有作为第一值的硅 - 硅元件与硅的组成比; 设置在所述第一绝缘膜的侧面上的氧化硅膜; 以及设置在氧化硅膜的表面上并具有作为第二值的非硅元素与硅的组成比的第二绝缘膜。第一个值小于第二个值。

7. 发明申请

US20130277640A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20130277640A1
公开(公告)日：2013-10-24
申请号：US13838722
申请日：2013-03-15
申请人： Kabushiki Kaisha Toshiba
发明人： Jun NISHIMURA , Nobuaki Yasutake , Kei Sakamoto , Takayuki Okamura
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2481 , H01L27/2409 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1641 , H01L45/1675
摘要： A non-volatile semiconductor memory device includes a cell array layer including a first wire, one or more memory cells stacked on the first wire, and a second wire formed on the memory cell so as to cross the first wire, wherein the memory cell includes a current rectifying element and a variable resistance element, and an atomic composition ratio of nitrogen is higher than that of oxygen in a part of a sidewall of the current rectifying element.
摘要翻译：一种非易失性半导体存储器件包括：单元阵列层，包括第一布线，堆叠在第一布线上的一个或多个存储单元，以及形成在存储单元上的第二布线，以便跨越第一布线，其中存储单元包括电流整流元件和可变电阻元件，并且氮的原子组成比高于当前整流元件的侧壁的一部分中的氧的原子组成比。

8. 发明申请

US20170077120A1 SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20170077120A1
公开(公告)日：2017-03-16
申请号：US14970919
申请日：2015-12-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ryosuke SAWABE , Shigeki Kobayashi , Takamasa Okawa , Kei Sakamoto
IPC分类号： H01L27/115 , H01L21/02 , H01L21/768
CPC分类号： H01L27/11582 , H01L21/02532 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76877 , H01L23/485 , H01L27/11556 , H01L27/1157
摘要： A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列，其具有：在第一半导体层上沿第一方向布置的第一导电层; 第二导电层，其沿第一方向布置在第一导电层上方; 沿第一方向延伸的柱状第二半导体层; 以及将第一半导体层和第二导电层电连接的接触单元。接触单元具有含有作为第一金属的硅化物并与第一半导体层接触的第一膜; 并且包含第一金属的第二膜与第一膜接触，并且与第一半导体层接触，第一膜插入其间。

9. 发明授权

US09142288B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09142288B2
公开(公告)日：2015-09-22
申请号：US14563605
申请日：2014-12-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kei Sakamoto , Masaki Kondo , Nobuaki Yasutake , Takayuki Okamura
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0002 , G11C13/004 , G11C13/0069 , G11C2213/72
摘要： A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of first lines, a plurality of second lines, and memory cells disposed at each of intersections of the first lines and the second lines; and a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line, respectively. The control circuit is configured to apply a fifth voltage to one of the non-selected first lines that is adjacent to the selected first line, and apply a sixth voltage to one of the non-selected second lines that is adjacent to the selected second line.
摘要翻译：根据实施例的半导体存储器件包括：存储单元阵列，包括多个第一线，多条第二线和设置在第一线和第二线的每个交点处的存储单元; 以及控制电路，被配置为向所选择的第一线施加第一电压，将具有小于第一电压的电压值的第二电压施加到所选择的第二线，并将第三电压和第四电压施加到未选择的第一行和未选择的第二行。控制电路被配置为向与所选择的第一行相邻的未选择的第一行之一施加第五电压，并且将第六电压施加到与所选择的第二行相邻的未选择的第二行之一。

10. 发明申请

US20170077026A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20170077026A1
公开(公告)日：2017-03-16
申请号：US15077305
申请日：2016-03-22
申请人： Kabushiki Kaisha Toshiba
发明人： Takamasa OKAWA , Shigeki Kobayashi , Kei Sakamoto , Ryosuke Sawabe
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , H01L27/115
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76816 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L27/11556 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer. The second conductive layer has an end portion as a contact connection portion. A contact plug is connected to the contact connection portion. The contact plug extends in the laminating direction. The contact plug includes a first member and a second member. The first member extends in the laminating direction. The second member extends in a direction intersecting with the laminating direction inside the contact connection portion.
摘要翻译：根据实施例，半导体存储器件包括沿层叠方向设置在衬底上方的多个第一导电层。阶梯式布线区域包括电连接到第一导电层的第二导电层。第二导电层具有作为接触连接部的端部。触点插头连接到触点连接部分。接触塞在层叠方向上延伸。接触塞包括第一构件和第二构件。第一构件在层叠方向上延伸。第二构件在与接触连接部内部的层叠方向相交的方向上延伸。

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