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1. 发明申请

US20140126270A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140126270A1
公开(公告)日：2014-05-08
申请号：US14152530
申请日：2014-01-10
申请人： Kabushiki Kaisha Toshiba
发明人： Yoichi MINEMURA , Takayuki TSUKAMOTO , Hiroshi KANNO , Takamasa OKAWA
IPC分类号： G11C13/00
CPC分类号： G11C13/0002 , G11C11/1673 , G11C11/419 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/72
摘要： A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.
摘要翻译：存储单元阵列包括设置在第一线和第二线的交点处的存储单元，并且每个具有串联连接的整流元件和可变电阻元件。控制电路在执行改变保留数据的操作时，将第一电压施加到所选择的第一行，并将第二电压施加到所选择的第二行; 此外，将第三电压施加到未选择的第一线; 此外，将大于第三电压的第四电压施加到未选择的第二线。将第三电压和第四电压之间的差的绝对值设定为小于第一电压和第二电压之间的差的绝对值除以偏移电压的量。随着第一和第二电压之间的差的绝对值增加，偏移电压的值增加。

2. 发明申请

US20140063889A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20140063889A1
公开(公告)日：2014-03-06
申请号：US13778840
申请日：2013-02-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoichi MINEMURA , Takayuki TSUKAMOTO , Hiroshi KANNO , Takamasa OKAWA
IPC分类号： G11C13/00 , G11C5/06
CPC分类号： G11C13/0002 , G11C5/06 , G11C8/08 , G11C13/00 , G11C13/0023 , G11C13/0028 , G11C13/003 , G11C2213/72
摘要： A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including first lines, second lines, and memory cells provided at each of intersections of the first lines and the second lines; and a control unit including a row control circuit, a first column control circuit provided on a side of one ends of the second lines, and a second column control circuit provided on a side of the other ends of the second lines, the control unit, during an access operation, controlling a potential of the first lines and the second lines such that a bias, which is lower than that applied to a certain unselected memory cell, is applied to those of unselected memory cells that are located more toward a center of the memory cell array in the column direction than the certain unselected memory cell.
摘要翻译：根据实施例的非易失性半导体存储器件包括：包括设置在第一线和第二线的每个交点处的第一线，第二线和存储单元的存储单元阵列; 以及控制单元，包括行控制电路，设置在所述第二线的一端的一侧的第一列控制电路和设置在所述第二线的另一端的一侧的第二列控制电路，所述控制单元，在访问操作期间，控制第一行和第二行的电位，使得低于施加到某个未选择的存储单元的偏移被施加到未选择的存储单元的偏置存储单元阵列在列方向上比某些未选择的存储单元。

3. 发明申请

US20160276353A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20160276353A1
公开(公告)日：2016-09-22
申请号：US14816431
申请日：2015-08-03
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeki KOBAYASHI , Kei SAKAMOTO , Takamasa OKAWA , Ryosuke SAWABE
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11565
摘要： A stacked body is disposed so as cover a periphery of a semiconductor columnar portion and includes a conductive layer and an inter-layer insulating layer stacked alternately in a stacking direction on a semiconductor substrate. An epitaxial layer is disposed on a surface of the semiconductor substrate and is electrically connected to a lower end of the semiconductor columnar portion. The semiconductor columnar portion comprises: an insulating film core; and a semiconductor portion disposed so as to cover a periphery of the insulating film core and electrically connected to the epitaxial layer at a lower end portion. The epitaxial layer includes a concave portion in a surface thereof, and the insulating film core has a lower end thereof positioned inside the concave portion.
摘要翻译：叠层体设置为覆盖半导体柱状部分的周围，并且包括在半导体衬底上沿堆叠方向交替堆叠的导电层和层间绝缘层。外延层设置在半导体衬底的表面上并与半导体柱状部分的下端电连接。半导体柱状部分包括：绝缘膜芯; 以及半导体部，其设置成覆盖绝缘膜芯的周边，并且在下端部与外延层电连接。外延层在其表面包括凹部，绝缘膜芯的下端位于凹部内部。

4. 发明申请

US20170077026A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20170077026A1
公开(公告)日：2017-03-16
申请号：US15077305
申请日：2016-03-22
申请人： Kabushiki Kaisha Toshiba
发明人： Takamasa OKAWA , Shigeki Kobayashi , Kei Sakamoto , Ryosuke Sawabe
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , H01L27/115
CPC分类号： H01L21/76843 , H01L21/76805 , H01L21/76816 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L27/11556 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer. The second conductive layer has an end portion as a contact connection portion. A contact plug is connected to the contact connection portion. The contact plug extends in the laminating direction. The contact plug includes a first member and a second member. The first member extends in the laminating direction. The second member extends in a direction intersecting with the laminating direction inside the contact connection portion.
摘要翻译：根据实施例，半导体存储器件包括沿层叠方向设置在衬底上方的多个第一导电层。阶梯式布线区域包括电连接到第一导电层的第二导电层。第二导电层具有作为接触连接部的端部。触点插头连接到触点连接部分。接触塞在层叠方向上延伸。接触塞包括第一构件和第二构件。第一构件在层叠方向上延伸。第二构件在与接触连接部内部的层叠方向相交的方向上延伸。

5. 发明申请

US20150228337A1 SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20150228337A1
公开(公告)日：2015-08-13
申请号：US14306843
申请日：2014-06-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takamasa OKAWA , Takayuki Tsukamoto , Yoichi Minemura , Hiroshi Kanno , Atsushi Yoshida , Hideyuki Tabata
IPC分类号： G11C13/00 , G11C5/02
CPC分类号： G11C13/0035 , G11C5/02 , G11C7/18 , G11C13/0002 , G11C13/0026 , G11C29/024 , G11C2029/5006 , G11C2213/71 , H01L27/101
摘要： A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.
摘要翻译：一种半导体存储器件，包括：沿垂直于衬底的第一方向设置的第一线，并沿与衬底平行的第二方向延伸; 第二线沿第二方向设置并且被配置为在第一方向上延伸，第二线与第一线相交; 以及设置在第一线和第二线的交叉点处并且每个包括可变电阻元件的存储单元。此外，第三线在与第一和第二方向正交的第三方向上延伸。选择晶体管连接在第二和第三线之间。控制电路控制施加到第一和第三线和选择晶体管的电压。控制电路使至少一个选择晶体管导通，从而检测在第三线中流动的电流，并根据检测结果确定选择晶体管的劣化状态。

6. 发明申请

US20150221368A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20150221368A1
公开(公告)日：2015-08-06
申请号：US14305371
申请日：2014-06-16
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroshi KANNO , Takayuki TSUKAMOTO , Takamasa OKAWA , Atsushi YOSHIDA
IPC分类号： G11C13/00 , H01L45/00
CPC分类号： H01L27/249 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2213/71 , H01L27/2454 , H01L45/085 , H01L45/1233 , H01L45/146
摘要： A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括：堆叠的多个第一导电层; 存储层，设置在所述多个所述第一导电层的侧面上; 以及经由存储层与多个第一导电层的侧表面接触的第二导电层。设置在第一位置处的第一导电层的厚度大于设置在第二位置的第一导电层的厚度。控制电路被配置为对所选择的第一导电层施加第一电压。控制电路基于所选择的第一导电层的位置来改变第一电压的值。

7. 发明申请

US20150117089A1 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US20150117089A1
公开(公告)日：2015-04-30
申请号：US14305503
申请日：2014-06-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoichi MINEMURA , Takayuki TSUKAMOTO , Hiroshi KANNO , Takamasa OKAWA , Atsushi YOSHIDA , Hideyuki TABATA
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C2013/0054 , G11C2013/0076 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79
摘要： A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes first lines and second lines intersecting each other, a third line commonly connecting to the first lines, memory cells disposed at intersections of the first lines and the second lines, respectively. The control circuit is configured to execute a state determining operation detecting a voltage of the third line, and adjust a voltage applied to the first lines and the second lines during a resetting operation or a setting operation based on a result of the state determining operation. The resetting operation raises a resistance value of the variable resistance element. The setting operation lowers the resistance value of the variable resistance element.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括彼此相交的第一行和第二行，通常连接到第一行的第三行，分别设置在第一行和第二行的交叉处的存储单元。控制电路被配置为执行检测第三线的电压的状态确定操作，并且在基于状态确定操作的结果的复位操作或设置操作期间调整施加到第一线路和第二线路的电压。复位操作提高了可变电阻元件的电阻值。设定动作降低可变电阻元件的电阻值。

8. 发明申请

US20150103582A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20150103582A1
公开(公告)日：2015-04-16
申请号：US14178636
申请日：2014-02-12
申请人： Kabushiki Kaisha Toshiba
发明人： Takamasa OKAWA , Takayuki TSUKAMOTO , Yoichi MINEMURA , Hiroshi KANNO , Atsushi YOSHIDA , Hideyuki TABATA
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/249 , G11C13/0002 , G11C13/0026 , G11C13/0069 , G11C2013/0073 , G11C2213/71 , H01L27/2454 , H01L45/04 , H01L45/12 , H01L45/1226 , H01L45/146
摘要： This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.
摘要翻译：该半导体存储器件包括存储单元阵列，其包括：多个第一线; 与所述多个第一线相交的多个第二线; 多个存储单元，各自设置在所述多个第一线和所述多条第二线的交点处，并且包括可变电阻元件; 以及选择晶体管，其分别连接到所述多条第一线的端部。选择晶体管包括栅电极，栅极绝缘膜和导电层。此外，该导电层的一端连接到第一线的端部，并且由第一线和导电层之间连接由非线性材料构成的非线性电阻层。

9. 发明申请

US20150014622A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20150014622A1
公开(公告)日：2015-01-15
申请号：US14107442
申请日：2013-12-16
申请人： Kabushiki Kaisha Toshiba
发明人： Hiroshi KANNO , Yoichi MINEMURA , Takayuki TSUKAMOTO , Takamasa OKAWA , Atsushi YOSHIDA , Hideyuki TABATA
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/085 , H01L45/10 , H01L45/1226 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1675
摘要： According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.
摘要翻译：根据实施例，非易失性存储器件包括沿第一方向延伸的第一布线，沿与第一方向正交的第二方向延伸的第二布线。该设备包括第三布线，以及第一和第二存储器。第三配线在与第一方向交叉的第三方向上延伸并且与第二方向垂直，并且在第二布线的两侧沿第二方向对齐。第一存储器设置在第三布线对和第二布线中的一个之间，所述一对第三布线跨越第二布线彼此面对。第二存储器设置在第三布线对和第二布线中的另一个之间。第二布线具有与第一存储器接触的第一部分和与第二存储器接触的第二部分之间的块部分。

10. 发明申请

US20140355326A1 NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：非易失性存储器件
公开(公告)号：US20140355326A1
公开(公告)日：2014-12-04
申请号：US14022485
申请日：2013-09-10
申请人： Kabushiki Kaisha Toshiba
发明人： Takamasa OKAWA , Takayuki TSUKAMOTO , Yoichi MINEMURA , Hiroshi KANNO , Atsushi YOSHIDA
IPC分类号： G11C13/00 , G11C5/06
CPC分类号： G11C13/0002 , G11C5/063 , G11C29/025 , G11C29/808
摘要： According to one embodiment, a non-volatile memory device includes: a plurality of first interconnects, and each of the first interconnects extending in a first direction; a plurality of second interconnects, and each of the second interconnects extending in a second direction intersecting with the first direction; a memory cell connected between each of the plurality of first interconnects and each of the plurality of second interconnects, the memory cell including a memory layer and a diode connected to the memory layer; and a control circuit capable of selecting a selection first interconnect among the first interconnects, selecting a selection second interconnect among the second interconnects, and selecting a selection memory cell connected to both the selection first interconnect and the selection second interconnect.
摘要翻译：根据一个实施例，非易失性存储器件包括：多个第一互连件，并且每个第一互连件沿第一方向延伸; 多个第二互连，并且所述第二互连中的每一个在与所述第一方向相交的第二方向上延伸; 连接在所述多个第一互连中的每一个与所述多个第二互连中的每一个之间的存储单元，所述存储单元包括连接到所述存储层的存储层和二极管; 以及控制电路，其能够选择所述第一互连中的选择第一互连，选择所述第二互连中的选择第二互连，以及选择连接到所述选择第一互连和所述选择第二互连的选择存储单元。

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