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1. 发明授权

US09633745B2 Semiconductor memory device 有权
公开(公告)号：US09633745B2
公开(公告)日：2017-04-25
申请号：US15185671
申请日：2016-06-17
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Abe , Masanobu Shirakawa , Mizuho Yoshida , Takuya Futatsuyama
IPC分类号： G11C16/04 , G11C16/34 , G11C11/56 , G11C16/10 , G11C16/32 , G11C16/08 , G11C16/16 , G11C29/42
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/32 , G11C16/3445 , G11C16/3481 , G11C29/42 , G11C2211/5621 , G11C2211/5648
摘要： A semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

2. 发明授权

US09612762B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US09612762B2
公开(公告)日：2017-04-04
申请号：US15166895
申请日：2016-05-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takuya Futatsuyama
IPC分类号： G11C16/04 , G06F3/06 , G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G06F3/061 , G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G11C11/5628 , G11C16/0408 , G11C16/045 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5648
摘要： A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

3. 发明授权

US09214238B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09214238B2
公开(公告)日：2015-12-15
申请号：US14474307
申请日：2014-09-02
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takuya Futatsuyama , Masanobu Shirakawa , Kenichi Abe
IPC分类号： G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： A semiconductor memory device includes first to fourth memory cells that are stacked above a semiconductor substrate, first to fourth word lines that are connected to gates of the first to fourth memory cells, respectively, and a row decoder that applies voltages to the first to fourth word lines. The row decoder applies a first programming voltage to the first word line during a write operation performed on the first memory cell, applies the first programming voltage to the second word line during a write operation performed on the second memory cell, applies a second programming voltage to the third word line during a write operation performed on the third memory cell, and applies the second programming voltage to the fourth word line during a write operation performed on the fourth memory cell. The second programming voltage is higher than the first programming voltage.
摘要翻译：一种半导体存储器件包括堆叠在半导体衬底之上的第一至第四存储单元，分别连接到第一至第四存储单元的栅极的第一至第四字线以及向第一至第四存储单元施加电压的行解码器字线。行解码器在对第一存储单元执行的写入操作期间向第一字线施加第一编程电压，在对第二存储单元执行的写入操作期间将第一编程电压施加到第二字线，施加第二编程电压在对第三存储器单元执行的写入操作期间将第二编程电压施加到第四字线，并且在对第四存储器单元执行的写入操作期间将第二编程电压施加到第四字线。第二编程电压高于第一编程电压。

4. 发明授权

US08772940B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08772940B2
公开(公告)日：2014-07-08
申请号：US13762787
申请日：2013-02-08
申请人： Kabushiki Kaisha Toshiba
发明人： Kenichi Abe , Takuya Futatsuyama , Jumpei Sato
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/823871 , H01L21/823892 , H01L23/485 , H01L23/528 , H01L23/5283 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.
摘要翻译：在半导体器件中，第一接触扩散层位于第一阱中，以连接到第一阱，并且在第一阱中的第一晶体管的沟道宽度方向上延伸。第一接触扩散层位于第一阱中，以与第一阱电连接并在第一晶体管的沟道长度方向上延伸。第一接触扩散层的第一接触部具有从基板的上方观察时的通道宽度方向的直径大于沟道长度方向的直径的形状。在第二接触扩散层上的第二接触具有沟道宽度方向的直径小于第一接触部的直径的形状，并且当从第一接触扩散层观察时，通道长度方向上的直径几乎等于第一接触的直径在基材之上。布线通过第二触点与第一晶体管电连接。

5. 发明授权

US09799403B2 Semiconductor memory device 有权
公开(公告)号：US09799403B2
公开(公告)日：2017-10-24
申请号：US15174849
申请日：2016-06-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa , Takuya Futatsuyama , Kenichi Abe , Hiroshi Nakamura , Keisuke Yonehama , Atsuhiro Sato , Hiroshi Shinohara , Yasuyuki Baba , Toshifumi Minami
IPC分类号： G11C16/04 , G11C16/14 , H01L27/1157 , H01L27/11582 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/42 , G11C16/34
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3445 , G11C29/42 , H01L27/1157 , H01L27/11582
摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

6. 发明授权

US09659663B2 Semiconductor memory device 有权
公开(公告)号：US09659663B2
公开(公告)日：2017-05-23
申请号：US14645740
申请日：2015-03-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa , Takuya Futatsuyama , Koji Hosono
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3427 , G11C16/3459 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line coupled to the first memory cell; and a second word line coupled to the second memory cell. When data is read from the first memory cell, a first voltage and a second voltage is applied to the first word line. A voltage of the second word line changes a first number of times while the first voltage is applied to the first word line, and the voltage changes a second number of times different from the first number of times while the second voltage is applied to the first word line.

7. 发明申请

US20150243358A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20150243358A1
公开(公告)日：2015-08-27
申请号：US14707908
申请日：2015-05-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takuya Futatsuyama
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G06F3/061 , G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G11C11/5628 , G11C16/0408 , G11C16/045 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5648
摘要： A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.
摘要翻译：非易失性半导体存储器件包括：单元单元，包括第一和第二选择栅极晶体管;以及存储器串，设置在第一和第二选择栅极晶体管之间，并且由多个串行连接的电可擦除可编程存储器单元组成，可操作以存储有效数据; 以及数据写入电路，用于将数据写入存储单元，其中存储器串两端的至少一个存储单元的编程级数低于其他存储单元的编程级数，数据写入电路将第一级程序执行到具有比第一级程序之后的其它存储单元的编程级数低于其它存储单元的程序级数的存储单元。

8. 发明授权

US09047951B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09047951B2
公开(公告)日：2015-06-02
申请号：US13841222
申请日：2013-03-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takuya Futatsuyama
IPC分类号： G11C7/06 , G11C16/04 , G11C16/06 , G11C16/26
CPC分类号： G11C16/04 , G11C7/06 , G11C16/0483 , G11C16/06 , G11C16/26
摘要： According to an embodiment, sense amplifiers are arranged one by one within an arrangement width of k bit lines in a direction of the bit lines, and determine data stored in the memory cells, based on potentials of the respective bit lines. Transistors constituting the sense amplifier are arranged one by one within an arrangement width of the sense amplifier in the direction of the bit lines. A gate length direction of the transistors is identical to the direction of the bit lines. A longer side direction of a contact electrode connected to an active area of the transistor is identical to the direction of the bit lines.
摘要翻译：根据实施例，读出放大器在位线的方向上的k位线的布置宽度内逐个布置，并且基于各位线的电位来确定存储在存储单元中的数据。构成读出放大器的晶体管在位线的方向上在读出放大器的布置宽度内逐个排列。晶体管的栅极长度方向与位线的方向相同。与晶体管的有源区连接的接触电极的长边方向与位线的方向相同。

9. 发明授权

US09892040B2 Semiconductor memory device 有权
公开(公告)号：US09892040B2
公开(公告)日：2018-02-13
申请号：US14841459
申请日：2015-08-31
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masanobu Shirakawa , Takuya Futatsuyama , Kenichi Abe
IPC分类号： G06F12/08 , G06F12/0811 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/30 , G11C11/56 , G11C8/08 , G11C29/02 , G06F12/0868 , G11C16/26 , G11C16/16 , G11C29/12
CPC分类号： G06F12/0811 , G06F12/0868 , G06F2212/283 , G11C8/08 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/30 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A semiconductor memory device includes: a memory cell array including memory strings, one of the memory strings including memory cells; word lines commonly connected to the memory strings; and a controller configured to execute a write operation and a read operation on a page, the page being stored in memory cells connected to one of the word lines. The controller is configured to measure a cell current flowing in the memory string, and adjust a write voltage applied to a word line, based on a result of the cell current.

10. 发明授权

US09378827B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US09378827B2
公开(公告)日：2016-06-28
申请号：US14707908
申请日：2015-05-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takuya Futatsuyama
IPC分类号： G11C16/06 , G11C16/10 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G06F3/061 , G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G11C11/5628 , G11C16/0408 , G11C16/045 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5648
摘要： A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

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