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1. 发明授权

US10424377B2 Semiconductor integrated circuit having programmable logic device and resistive change elements 有权
公开(公告)号：US10424377B2
公开(公告)日：2019-09-24
申请号：US15907711
申请日：2018-02-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yinghao Ho , Masato Oda , Kosuke Tatsumura , Shinichi Yasuda
IPC分类号： G11C13/00 , H01L23/525 , H01L27/24 , H01L45/00
摘要： A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to corresponding one of the fifth wirings.

2. 发明授权

US09525422B2 Reconfigurable semiconductor integrated circuit and electronic device 有权
标题翻译：可重构半导体集成电路和电子设备
公开(公告)号：US09525422B2
公开(公告)日：2016-12-20
申请号：US15072890
申请日：2016-03-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masato Oda
IPC分类号： H03K19/003 , H03K19/177 , H03K19/173 , G11C13/00 , G11C11/41 , G11C29/50 , G11C17/18
CPC分类号： H03K19/1776 , G11C11/41 , G11C13/0069 , G11C17/165 , G11C17/18 , G11C2029/5006 , H03K19/1737 , H03K19/17728
摘要： According to an embodiment, a reconfigurable semiconductor integrated circuit includes memories connected in parallel, a logic circuit whose logic is defined according to data output of one of the memories, a signal output unit, and a switching unit. The signal output unit includes output terminals corresponding to the respective memories. Each terminal outputs a selection signal for enabling the data output or a non-selection signal for disabling the data output to the logic circuit. The signal output unit is configured to output the selection signal in a cyclic manner over the terminals so that one terminal outputs the selection signal and the others output the non-selection signal. The switching unit is configured to set a route between a first output terminal and a second output terminal of the terminals to an open state or a closed state. The route bypasses at least a single output terminal.
摘要翻译：根据实施例，可重构半导体集成电路包括并联连接的存储器，逻辑电路的逻辑根据存储器之一的数据输出，信号输出单元和切换单元来定义。信号输出单元包括对应于各个存储器的输出端子。每个终端输出用于启用数据输出的选择信号或用于禁止输出到逻辑电路的数据的非选择信号。信号输出单元被配置为以循环的方式在端子上输出选择信号，使得一个终端输出选择信号，而其它终端输出非选择信号。开关单元被配置为将终端的第一输出端子和第二输出端子之间的路径设置为打开状态或关闭状态。该路由至少绕过一个输出终端。

3. 发明申请

US20160112049A1 PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA 审中-公开
公开(公告)号：US20160112049A1
公开(公告)日：2016-04-21
申请号：US14983968
申请日：2015-12-30
申请人： Kabushiki Kaisha Toshiba
发明人： Shinichi Yasuda , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , H03K19/018585 , H03K19/0948 , H03K19/177 , H03K19/1776
摘要： A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.

4. 发明申请

US20150214950A1 PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA 有权
标题翻译：可编程逻辑电路和非易失性FPGA
公开(公告)号：US20150214950A1
公开(公告)日：2015-07-30
申请号：US14602306
申请日：2015-01-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda
IPC分类号： H03K19/0185 , H03K19/177 , H03K19/0948
CPC分类号： H03K19/17728 , H03K19/018585 , H03K19/0948 , H03K19/177 , H03K19/1776
摘要： A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.
摘要翻译：可编程逻辑电路包括：第一至第三布线，第二布线与第一布线交叉; 以及提供在相交区域中的单元，包括第一晶体管和可编程器件的单元中的至少一个具有第一和第二端子，所述第一端子连接到所述第一晶体管的源极和漏极中的一个，所述第二端子连接到第二布线中的一个，源极和漏极中的另一个连接到第一布线中的一个，第一晶体管的栅极连接到第三布线之一。每个第一截止晶体管的源极和漏极中的一个连接到第二布线中的一个，并且每个第一CMOS反相器的输入端子连接到源极和漏极中的另一个。

5. 发明申请

US20190043581A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20190043581A1
公开(公告)日：2019-02-07
申请号：US15912596
申请日：2018-03-06
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinichi Yasuda , Masato Oda , Kosuke Tatsumura
IPC分类号： G11C14/00 , G11C11/419 , G11C5/06 , H03K19/173
CPC分类号： G11C14/0054 , G11C5/06 , G11C5/063 , G11C11/417 , G11C11/419 , G11C17/165 , H03K19/1735 , H03K19/1737 , H03K19/17728
摘要： A semiconductor integrated circuit according to an embodiment includes: first to third wiring lines; first memory elements disposed in a cross region between the first wiring lines and the second wiring lines; second memory elements disposed in a cross region between the first wiring lines and the third wiring lines; a first write control circuit connected to the first wiring lines: a first circuit connected to one of the second wiring lines and supplying a first potential; a second circuit connected to the other one of the second wiring lines and supplying a second potential lower than the first potential; SRAM cells connected to the third wiring lines; and a selection circuit including input terminals electrically connected to the first wiring lines and an output terminal, the selection circuit connecting one of the input terminals to the output terminal in accordance with an input signal.

6. 发明授权

US09438243B2 Programmable logic circuit and nonvolatile FPGA 有权
公开(公告)号：US09438243B2
公开(公告)日：2016-09-06
申请号：US14983968
申请日：2015-12-30
申请人： Kabushiki Kaisha Toshiba
发明人： Shinichi Yasuda , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17728 , H03K19/018585 , H03K19/0948 , H03K19/177 , H03K19/1776
摘要： A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.

7. 发明申请

US20160035419A1 RECONFIGURABLE CIRCUIT AND METHOD OF PROGRAMMING THE SAME 有权
标题翻译：可重构电路及其编程方法
公开(公告)号：US20160035419A1
公开(公告)日：2016-02-04
申请号：US14884215
申请日：2015-10-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Koichiro ZAITSU , Shinichi Yasuda , Kosuke Tatsumura , Mari Matsumoto , Masato Oda , Reika Ichihara
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C2013/0078 , G11C2213/77 , H03K19/1776
摘要： A reconfigurable circuit according to an embodiment includes: first wiring lines; second wiring lines crossing the first wiring lines; resistive change elements disposed in intersection regions of the first and second wiring lines, each of the resistive change elements including a first terminal connected to the one of the first wiring lines and a second terminal connected to the one of the second wiring lines, and being switchable between a low-resistance state and a high-resistance state; a first control circuit controlling a voltage to be applied to the first wiring lines; a second control circuit controlling a voltage to be applied to the second wiring lines; and current limiting elements corresponding to the second wiring lines, and controlling current flowing through the resistive change elements connected to the corresponding second wiring line.
摘要翻译：根据实施例的可重新配置电路包括：第一布线; 与第一布线相交的第二布线; 电阻变化元件设置在第一和第二布线的交叉区域中，每个电阻变化元件包括连接到第一布线中的一个的第一端子和连接到第二布线中的一条布线的第二端子，并且可在低电阻状态和高电阻状态之间切换; 控制施加到第一布线的电压的第一控制电路; 控制要施加到第二布线的电压的第二控制电路; 以及对应于第二布线的电流限制元件，以及控制流过连接到对应的第二布线的电阻变化元件的电流。

8. 发明申请

US20130222011A1 PROGRAMMABLE LOGIC SWITCH 有权
标题翻译：可编程逻辑开关
公开(公告)号：US20130222011A1
公开(公告)日：2013-08-29
申请号：US13856448
申请日：2013-04-04
申请人： Kabushiki Kaisha Toshiba
发明人： Koichiro Zaitsu , Kosuke Tatsumura , Mari Matsumoto , Shinichi Yasuda , Masato Oda , Haruka Kusai , Kiwamu Sakuma
IPC分类号： H03K19/0185
CPC分类号： H03K19/018585 , G11C5/146 , G11C16/10 , G11C16/12 , H03K19/1737
摘要： One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.
摘要翻译：一个实施例提供一种可编程逻辑开关，其中在同一个阱中形成第一非易失性存储器和第二非易失性存储器，并且其中将第一非易失性存储器从擦除状态改变为写入状态，并使第二非易失性存储器处于擦除状态时，将第一写入电压施加到与第一和第二非易失性存储器的栅电极连接的第一线，第二写入电压被施加到连接到第一非易失性存储器中的源极的第二线，并且第三写入低于第二写入电压的电压被施加到连接到第二非易失性存储器的源极的第四线路。

9. 发明授权

US10360333B1 Configuration memory circuit 有权
公开(公告)号：US10360333B1
公开(公告)日：2019-07-23
申请号：US16129126
申请日：2018-09-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinichi Yasuda , Masato Oda
IPC分类号： G06F17/50 , G06F7/12 , G11C7/12 , G11C8/08 , G11C16/04 , G11C8/14 , G11C11/412 , G11C7/18
摘要： A configuration memory circuit according to an embodiment includes: a first and second wirings; and a first to eighth transistors, the first and fourth transistors having a first-conductive-type, the second, third, fifth, and sixth transistors having a second-conductive-type, the first to third transistors being connected in series, the fourth to sixth transistors being connected in series, gates of the first and third transistors being connected to the first wiring, one of a source and a drain of the seventh transistor, and the first wiring, a gate of the second transistor being connected to a third wiring, gates of the fourth and sixth transistors being connected to the second wiring, one of a source and a drain of the eighth transistor, and the second wiring, a gate of the fifth transistor being connected to the third wiring, gates of the seventh and eighth transistors being connected to a fifth wiring.

10. 发明授权

US09948305B2 Integrated circuit and electronic apparatus 有权
公开(公告)号：US09948305B2
公开(公告)日：2018-04-17
申请号：US15445450
申请日：2017-02-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masato Oda , Shinichi Yasuda
IPC分类号： H03K19/177 , H01L25/00 , H03K19/173 , H01L23/525
CPC分类号： H03K19/1737 , H01L23/5252 , H03K19/1735 , H03K19/17728 , H03K19/1776
摘要： An integrated circuit of an embodiment includes: a first to third wiring lines; a first and second input terminals connected to the second and third wiring lines respectively; a first and second control terminals; a first switch element disposed between the first and second wiring lines, the first switch element including a first and second terminals connected to the first and second wiring lines respectively; a second switch element disposed between the first and third wiring lines, the second switch element including a third and fourth terminals connected to the first and fourth terminals connected to the first and third wiring lines respectively; a first transistor including a source and a drain, one of the source and the drain being connected to the first wiring line; a select circuit including a fifth to eighth terminals; and a logic circuit including a ninth to eleventh terminals.

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