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1. 发明申请

US20170271404A1 RESISTIVE CHANGE ELEMENT, NON-VOLATILE STORAGE DEVICE, AND PROGRAMMABLE LOGIC DEVICE 审中-公开
公开(公告)号：US20170271404A1
公开(公告)日：2017-09-21
申请号：US15266668
申请日：2016-09-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yinghao HO , Koichiro Zaitsu , Shinichi Yasuda
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/2409 , G11C13/0038 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/77 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A programmable logic device according to an embodiment includes: a plurality of first and second wiring lines; a plurality of resistive change elements each including a first electrode containing Ni and connected to corresponding one of the first wiring lines, a second electrode containing TiN and connected to corresponding one of the second wiring lines, a resistive change layer containing a hafnium oxide and arranged between the first electrode and the second electrode, and an insulation layer arranged between the resistive change layer and the second electrode, the insulation layer including at least one of an aluminum oxide, an iron oxide, a titanium oxide, a copper oxide, a nickel oxide, a tantalum oxide, a tungsten oxide, a chromium oxide, a rhenium oxide, and a hafnium oxynitride.

2. 发明授权

US09620203B2 Nonvolatile memory integrated circuit with built-in redundancy 有权
公开(公告)号：US09620203B2
公开(公告)日：2017-04-11
申请号：US14849047
申请日：2015-09-09
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Haiyang Peng , Koichiro Zaitsu , Shinichi Yasuda
IPC分类号： G11C11/00 , G11C11/36 , G11C13/00 , G11C17/16 , G11C17/18 , G11C29/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C17/165 , G11C17/18 , G11C29/787 , G11C2213/15 , G11C2213/77 , G11C2213/78 , G11C2213/79
摘要： According to one embodiment, a semiconductor integrated circuit includes a memory cell including first and second electrodes and a resistance change film therebetween, and a control circuit controlling a potential difference between the first and second electrodes. The control circuit reversibly changes the memory cell to a first resistive state by applying a first potential to the first electrode and by applying a second potential smaller than the first potential to the second electrode. The control circuit reversibly changes the memory cell to a second resistive state by applying a third potential to the first electrode and by applying a fourth potential smaller than the third potential to the second electrode.

3. 发明申请

US20160112049A1 PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA 审中-公开
公开(公告)号：US20160112049A1
公开(公告)日：2016-04-21
申请号：US14983968
申请日：2015-12-30
申请人： Kabushiki Kaisha Toshiba
发明人： Shinichi Yasuda , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , H03K19/018585 , H03K19/0948 , H03K19/177 , H03K19/1776
摘要： A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.

4. 发明申请

US20150214950A1 PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA 有权
标题翻译：可编程逻辑电路和非易失性FPGA
公开(公告)号：US20150214950A1
公开(公告)日：2015-07-30
申请号：US14602306
申请日：2015-01-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda
IPC分类号： H03K19/0185 , H03K19/177 , H03K19/0948
CPC分类号： H03K19/17728 , H03K19/018585 , H03K19/0948 , H03K19/177 , H03K19/1776
摘要： A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.
摘要翻译：可编程逻辑电路包括：第一至第三布线，第二布线与第一布线交叉; 以及提供在相交区域中的单元，包括第一晶体管和可编程器件的单元中的至少一个具有第一和第二端子，所述第一端子连接到所述第一晶体管的源极和漏极中的一个，所述第二端子连接到第二布线中的一个，源极和漏极中的另一个连接到第一布线中的一个，第一晶体管的栅极连接到第三布线之一。每个第一截止晶体管的源极和漏极中的一个连接到第二布线中的一个，并且每个第一CMOS反相器的输入端子连接到源极和漏极中的另一个。

5. 发明授权

US09691476B2 Multi-context configuration memory 有权
公开(公告)号：US09691476B2
公开(公告)日：2017-06-27
申请号：US14831193
申请日：2015-08-20
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kosuke Tatsumura , Mari Matsumoto , Masato Oda , Koichiro Zaitsu , Shinichi Yasuda
IPC分类号： G11C13/00 , G11C11/16 , H03K19/177 , G11C14/00
CPC分类号： G11C13/004 , G11C11/16 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0002 , G11C13/0004 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C14/009 , G11C2213/78 , H03K19/1776
摘要： According to one embodiment, an integrated circuit includes first and second data lines, a first memory cell includes first and second resistance changing elements connected in series between the first and second data lines and a first selection transistor including a drain connected to a connection node of the first and second resistance changing elements, and a second memory cell includes third and fourth resistance changing elements connected in series between the first and second data lines and a second selection transistor including a drain connected to a connection node of the third and fourth resistance changing elements.

6. 发明授权

US09514839B2 Nonvolatile memory, nonvolatile programmable logic switch including nonvolatile memory, and nonvolatile programmable logic circuit 有权
标题翻译：非易失性存储器，包括非易失性存储器的非易失性可编程逻辑开关和非易失性可编程逻辑电路
公开(公告)号：US09514839B2
公开(公告)日：2016-12-06
申请号：US14726884
申请日：2015-06-01
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mari Matsumoto , Kosuke Tatsumura , Koichiro Zaitsu , Shinichi Yasuda
IPC分类号： G11C17/16 , H01L27/112 , G11C16/10
CPC分类号： G11C17/16 , G11C16/10 , H01L27/11206
摘要： A nonvolatile memory according to an embodiment includes a memory cell, the memory cell including: a memory transistor including a source, a drain, a gate electrode disposed above a channel between the source and the drain, and a gate insulating film disposed between the channel and the gate electrode; and a fuse element disposed between the gate electrode and a wiring line to which the gate electrode of the memory transistor is connected.
摘要翻译：根据实施例的非易失性存储器包括存储单元，所述存储单元包括：存储晶体管，包括源极，漏极，设置在所述源极和漏极之间的沟道之上的栅电极，以及设置在所述沟道之间的栅极绝缘膜和栅电极; 以及设置在所述栅电极与所述存储晶体管的栅电极连接的布线之间的熔丝元件。

7. 发明授权

US09431104B2 Reconfigurable circuit and method of programming the same 有权
标题翻译：可重构电路和编程方法相同
公开(公告)号：US09431104B2
公开(公告)日：2016-08-30
申请号：US14884215
申请日：2015-10-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Koichiro Zaitsu , Shinichi Yasuda , Kosuke Tatsumura , Mari Matsumoto , Masato Oda , Reika Ichihara
IPC分类号： G11C11/00 , G11C13/00 , H03K19/177
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C2013/0078 , G11C2213/77 , H03K19/1776
摘要： A reconfigurable circuit according to an embodiment includes: first wiring lines; second wiring lines crossing the first wiring lines; resistive change elements disposed in intersection regions of the first and second wiring lines, each of the resistive change elements including a first terminal connected to the one of the first wiring lines and a second terminal connected to the one of the second wiring lines, and being switchable between a low-resistance state and a high-resistance state; a first control circuit controlling a voltage to be applied to the first wiring lines; a second control circuit controlling a voltage to be applied to the second wiring lines; and current limiting elements corresponding to the second wiring lines, and controlling current flowing through the resistive change elements connected to the corresponding second wiring line.
摘要翻译：根据实施例的可重新配置电路包括：第一布线; 与第一布线相交的第二布线; 电阻变化元件设置在第一和第二布线的交叉区域中，每个电阻变化元件包括连接到第一布线中的一个的第一端子和与第二布线中的一条线连接的第二端子，并且可在低电阻状态和高电阻状态之间切换; 控制施加到第一布线的电压的第一控制电路; 控制要施加到第二布线的电压的第二控制电路; 以及对应于第二布线的电流限制元件，以及控制流过连接到对应的第二布线的电阻变化元件的电流。

8. 发明申请

US20160203866A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
公开(公告)号：US20160203866A1
公开(公告)日：2016-07-14
申请号：US14988034
申请日：2016-01-05
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Koichiro Zaitsu , Kosuke Tatsumura , Masato Oda
IPC分类号： G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0026 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2213/33 , G11C2213/34 , G11C2213/77 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A semiconductor integrated circuit according to an embodiment includes: N (≧1) input wiring lines; M (≧1) output wiring lines; N first wiring lines corresponding to the N input wiring lines; K (>M) second wiring lines crossing the N first wiring lines; a plurality of first resistive change elements disposed at intersections of the first wiring lines and the second wiring lines, each of the first resistive change elements including a first electrode connecting to a corresponding one of the first wiring lines, a second electrode connecting to a corresponding one of the second wiring lines, and a first resistive change layer disposed between the first electrode and the second electrode; a first controller controlling a voltage applied to the first wiring lines; a second controller controlling a voltage applied to the second wiring lines; and a selection circuit selecting M second wiring lines from the K second wiring lines.

9. 发明授权

US09343150B2 Programmable logic device with resistive change memories 有权
标题翻译：具有电阻变化存储器的可编程逻辑器件
公开(公告)号：US09343150B2
公开(公告)日：2016-05-17
申请号：US14610305
申请日：2015-01-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Koichiro Zaitsu , Shinichi Yasuda
IPC分类号： G11C13/00 , H01L45/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0071 , H01L45/04 , H01L45/145 , H01L45/146 , H01L45/148
摘要： A programmable logic device includes: a first memory element including a first electrode connected to a first wiring line, a second electrode, and a first resistive change layer, a resistance between the first and second electrodes being changed from a low-resistance state to a high-resistance state by applying, to the second electrode, a voltage higher than a voltage applied to the first electrode; a second memory element including a third electrode connected to the second electrode, a fourth electrode connected to a second wiring line, and a second resistive change layer, a resistance between the third and fourth electrodes being changed from a low-resistance state to a high-resistance state by applying, to the fourth electrode, a voltage higher than a voltage applied to the third electrode; and a first transistor, of which a gate is connected to the second electrode and the third electrode.
摘要翻译：可编程逻辑器件包括：第一存储元件，包括连接到第一布线，第二电极和第一电阻变化层的第一电极，第一和第二电极之间的电阻从低电阻状态改变为向第二电极施加高于施加到第一电极的电压的电压的高电阻状态; 第二存储元件，包括连接到第二电极的第三电极，连接到第二布线的第四电极和第二电阻变化层，第三和第四电极之间的电阻从低电阻状态变为高电平向第四电极施加高于施加到第三电极的电压的电压; 以及第一晶体管，其栅极连接到第二电极和第三电极。

10. 发明授权

US09007838B2 Semiconductor integrated circuit having a permanently conductive non-volatile memory element 有权
标题翻译：具有永久导电的非易失性存储元件的半导体集成电路
公开(公告)号：US09007838B2
公开(公告)日：2015-04-14
申请号：US13776377
申请日：2013-02-25
申请人： Kabushiki Kaisha Toshiba
发明人： Koichiro Zaitsu , Kosuke Tatsumura
IPC分类号： G11C11/40 , H01L29/792 , H01L29/788 , H01L27/115 , H01L27/118 , G11C16/10
CPC分类号： H01L29/792 , G11C16/10 , H01L27/11526 , H01L27/11573 , H01L27/11803 , H01L29/7881
摘要： A semiconductor integrated circuit includes a transistor with a source region, a drain region, and a control gate electrode. The integrated circuit additionally includes a controller that selectively applies voltages to the control gate of the transistor. The controller may apply a first voltage that forms a permanent conductive path between the source and drain of the transistor.
摘要翻译：半导体集成电路包括具有源极区域，漏极区域和控制栅极电极的晶体管。集成电路还包括选择性地向晶体管的控制栅极施加电压的控制器。控制器可以施加在晶体管的源极和漏极之间形成永久导电路径的第一电压。

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