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1. 发明申请

US20130335147A1 Power Amplifier and Linearization Techniques Using Active and Passive Devices 有权
标题翻译：使用主动和被动设备的功率放大器和线性化技术
公开(公告)号：US20130335147A1
公开(公告)日：2013-12-19
申请号：US13880550
申请日：2011-10-20
申请人： Kai Xue Ma , Jiangmin Gu , Yang Lu , Kiat Seng Yeo
发明人： Kai Xue Ma , Jiangmin Gu , Yang Lu , Kiat Seng Yeo
IPC分类号： H03F3/21
CPC分类号： H03F3/21 , H03F1/0261 , H03F1/32 , H03F1/3211 , H03F1/56 , H03F3/191 , H03F3/195 , H03F3/245 , H03F3/60 , H03F2200/18 , H03F2200/222 , H03F2200/387
摘要： Designs and techniques for improving the linearity of the power amplifiers, especially of the non-linear types, operated in microwave and millimeter-wave frequency using method through purposely designed active transistors or passive devices or both, are disclosed. The techniques use the manipulation of transistors' cut-off frequencies (fT) design, attached loaded linearization stub and characteristics of space attenuation of microwave signals individually or in combination of them. The disclosed techniques provide the advantages to compromise the performance among linearity, gain and power consumption in a wide range of power amplifier types, such as Class- AB, B, C, D, E and F in the different application scenarios.
摘要翻译：公开了通过专门设计的有源晶体管或无源器件或两者在微波和毫米波频率使用方法中操作的功率放大器，特别是非线性型功率放大器的线性度的设计和技术。这些技术使用晶体管的截止频率（fT）设计，附加的负载线性化短截线和微波信号的空间衰减特性单独或组合的操作。所公开的技术提供了在各种功率放大器类型（例如不同应用场合中的类AB，B，C，D，E和F）中的线性度，增益和功率消耗之间的性能损害的优点。

2. 发明授权

US09337157B2 Miniature passive structures for ESD protection and input and output matching 有权
标题翻译：用于ESD保护和输入和输出匹配的微型无源结构
公开(公告)号：US09337157B2
公开(公告)日：2016-05-10
申请号：US13880481
申请日：2011-10-20
申请人： Kai Xue Ma , Yang Lu , Jiangmin Gu , Kiat Seng Yeo
发明人： Kai Xue Ma , Yang Lu , Jiangmin Gu , Kiat Seng Yeo
IPC分类号： H01L23/60 , H01L23/66 , H01L23/00
CPC分类号： H01L23/60 , H01L23/66 , H01L24/05 , H01L2223/6627 , H01L2223/6666 , H01L2924/13034 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A miniature passive structure for electrostatic discharge (ESD) protection and input/output (I/O) matching for a high frequency integrated circuit is provided. The miniature passive structure includes at least one shunt stub and at least one load line. The shunt stub(s) each provide a corresponding ESD discharge path. The load line(s) are coupled to the shunt stub(s) and provide loading effects for the shunt stub(s).
摘要翻译：提供了一种用于高频集成电路的静电放电（ESD）保护和输入/输出（I / O）匹配的微型无源结构。微型无源结构包括至少一个分流短截线和至少一个负载线。分流短截线各自提供相应的ESD放电路径。负载线耦合到分路短路，并为分路短路提供负载效应。

3. 发明授权

US09130511B2 Power amplifier and linearization techniques using active and passive devices 有权
标题翻译：功率放大器和使用有源和无源器件的线性化技术
公开(公告)号：US09130511B2
公开(公告)日：2015-09-08
申请号：US13880550
申请日：2011-10-20
申请人： Kai Xue Ma , Jiangmin Gu , Yang Lu , Kiat Seng Yeo
发明人： Kai Xue Ma , Jiangmin Gu , Yang Lu , Kiat Seng Yeo
IPC分类号： H03F3/191 , H03F3/21 , H03F1/02 , H03F1/32 , H03F1/56 , H03F3/195 , H03F3/24 , H03F3/60
CPC分类号： H03F3/21 , H03F1/0261 , H03F1/32 , H03F1/3211 , H03F1/56 , H03F3/191 , H03F3/195 , H03F3/245 , H03F3/60 , H03F2200/18 , H03F2200/222 , H03F2200/387
摘要： Designs and techniques for improving the linearity of the power amplifiers, especially of the non-linear types, operated in microwave and millimeter-wave frequency using method through purposely designed active transistors or passive devices or both, are disclosed. The techniques use the manipulation of transistors' cut-off frequencies (fT) design, attached loaded linearization stub and characteristics of space attenuation of microwave signals individually or in combination of them. The disclosed techniques provide the advantages to compromise the performance among linearity, gain and power consumption in a wide range of power amplifier types, such as Class-AB, B, C, D, E and F in the different application scenarios.
摘要翻译：公开了通过专门设计的有源晶体管或无源器件或两者在微波和毫米波频率使用方法中操作的功率放大器，特别是非线性型功率放大器的线性度的设计和技术。这些技术使用晶体管的截止频率（fT）设计，附加的负载线性化短截线和微波信号的空间衰减特性单独或组合的操作。所公开的技术提供了在各种功率放大器类型（例如不同应用场合中的AB类，B类，C，D，E和F类）的线性度，增益和功率消耗之间的性能损害的优点。

4. 发明申请

US20140049862A1 Miniature Passive Structures for ESD Protection and Input and Output Matching 有权
标题翻译：用于ESD保护和输入和输出匹配的微型被动结构
公开(公告)号：US20140049862A1
公开(公告)日：2014-02-20
申请号：US13880481
申请日：2011-10-20
申请人： Kai Xue Ma , Yang Lu , Jiangmin Gu , Kiat Seng Yeo
发明人： Kai Xue Ma , Yang Lu , Jiangmin Gu , Kiat Seng Yeo
IPC分类号： H01L23/60 , H01L23/66
CPC分类号： H01L23/60 , H01L23/66 , H01L24/05 , H01L2223/6627 , H01L2223/6666 , H01L2924/13034 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A miniature passive structure for electrostatic discharge (ESD) protection and input/output (I/O) matching for a high frequency integrated circuit is provided. The miniature passive structure includes at least one shunt stub and at least one load line. The shunt stub(s) each provide a corresponding ESD discharge path. The load line(s) are coupled to the shunt stub(s) and provide loading effects for the shunt stub(s).
摘要翻译：提供了一种用于高频集成电路的静电放电（ESD）保护和输入/输出（I / O）匹配的微型无源结构。微型无源结构包括至少一个分流短截线和至少一个负载线。分流短截线各自提供相应的ESD放电路径。负载线耦合到分路短路，并为分路短路提供负载效应。

5. 发明申请

US20160308676A1 RSA ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
标题翻译： RSA算法加速处理器，方法，系统和指令
公开(公告)号：US20160308676A1
公开(公告)日：2016-10-20
申请号：US15102637
申请日：2013-12-28
申请人： Yang LU , Xiangzheng SUN , Nan Stan QIAO , INTEL CORPORATION
发明人： Yang Lu , Xiangzheng Sun , Nan Qiao
IPC分类号： H04L9/30 , G06F9/30 , G06F7/72
CPC分类号： H04L9/302 , G06F7/722 , G06F7/723 , G06F9/30007 , G06F9/3017 , G09C1/00
摘要： A processor includes a decode unit to decode an instruction. The instruction indicates a first 64-bit source operand having a first 64-bit value, indicates a second 64-bit source operand having a second 64-bit value, indicates a third 64-bit source operand having a third 64-bit value, and indicates a fourth 64-bit source operand having a fourth 64-bit value. An execution unit is coupled with the decode unit. The execution unit is operable, in response to the instruction, to store a result. The result includes the first 64-bit value multiplied by the second 64-bit value added to the third 64-bit value added to the fourth 64-bit value. The execution unit may store a 64-bit least significant half of the result in a first 64-bit destination operand indicated by the instruction, and store a 64-bit most significant half of the result in a second 64-bit destination operand indicated by the instruction.
摘要翻译：处理器包括解码指令译码单元。该指令指示具有第一64位值的第一64位源操作数，指示具有第二64位值的第二64位源操作数，指示具有第三64位值的第三64位源操作数，并且指示具有第四个64位值的第四个64位源操作数。执行单元与解码单元耦合。执行单元响应于该指令可操作以存储结果。结果包括第一个64位值乘以加到第四个64位值的第三个64位值的第二个64位值。执行单元可以将结果的64位最不重要的一半存储在由指令指示的第一个64位目标操作数中，并将结果的64位最高有效的一半存储在第二个64位目标操作数中，指示。

6. 发明授权

US09450741B2 Method, system, and device for working on TDD cell 有权
标题翻译：用于TDD单元的方法，系统和设备
公开(公告)号：US09450741B2
公开(公告)日：2016-09-20
申请号：US13991897
申请日：2011-11-30
申请人： Yang Lu , Fangli Xu , Jing Liang
发明人： Yang Lu , Fangli Xu , Jing Liang
IPC分类号： H04L5/14 , H04W48/12 , H04B7/26 , H04W48/08
CPC分类号： H04L5/14 , H04B7/2656 , H04W48/08 , H04W48/12
摘要： Embodiments of the present application relate to the technical field of radio communication, and particularly to a method, system, and device for working on a TDD cell for enabling a UE to work on an asymmetric TDD cell. According to the embodiments of the present application, the method comprises: A network side device determining uplink parameter information of the asymmetric TDD cell; and the network side device putting the uplink parameter information into system information and sending the system information to a terminal to instruct the terminal to work on the corresponding asymmetric TDD cell according to the system information. In the embodiments of the present application, the uplink parameter information is added to the system information so that the terminal can work on the asymmetric TDD cell according to the system information, thereby improving the efficiency of the terminal.
摘要翻译：本申请的实施例涉及无线电通信的技术领域，特别涉及用于在TDD小区上工作以使UE能够在非对称TDD小区上工作的方法，系统和设备。根据本申请的实施例，该方法包括：确定不对称TDD小区的上行链路参数信息的网络侧设备; 网络侧设备将上行链路参数信息加入到系统信息中，并将系统信息发送到终端，以指示终端根据系统信息对相应的非对称TDD小区进行工作。在本申请的实施例中，将上行链路参数信息添加到系统信息，使得终端可以根据系统信息对非对称TDD小区进行工作，从而提高终端的效率。

7. 发明申请

US20160253538A1 Methods and Apparatus of Integrating Fingerprint Imagers with Touch Panels and Displays 审中-公开
公开(公告)号：US20160253538A1
公开(公告)日：2016-09-01
申请号：US14634826
申请日：2015-02-28
申请人： Yang Lu , Weidong Shi
发明人： Yang Lu , Weidong Shi
IPC分类号： G06K9/00 , G06F21/32 , G06F3/041
CPC分类号： G06K9/0002 , G06F1/1626 , G06F1/1643 , G06F1/1684 , G06F3/041 , G06F3/0412 , G06F3/0416 , G06F3/04886 , G06F21/32 , G06F2203/04103 , G06K9/00087 , G06K9/036
摘要： The present invention provides systems and methods of an apparatus that comprises a layer of fingerprint imagers, an addressing circuit, a fingerprint controller, an electronic storage devices, a layer of touch panel and a display panel. The touch panel behind the layer of fingerprint imagers can sense touch position when touched. The specific fingerprint imagers can be activated according to the touch panel coordinates when touched by a user. After fingerprint is captured, the system evaluates quality of the captured fingerprint and admits fingerprint for recognition when its quality is above a threshold value. User of a computing system can be accepted or rejected based on the comparison between the captured fingerprint and an authorized fingerprint list.

8. 发明授权

US09197027B2 Method for making laser module 有权
标题翻译：激光模块制作方法
公开(公告)号：US09197027B2
公开(公告)日：2015-11-24
申请号：US13542478
申请日：2012-07-05
申请人： Qingyang Xu , Yang Lu , Hongping Su , Xiangyang Li
发明人： Qingyang Xu , Yang Lu , Hongping Su , Xiangyang Li
IPC分类号： H01S1/02 , H01S3/02 , H01S3/042 , H01S3/07 , H01S3/109 , H01S3/16
CPC分类号： H01S3/025 , H01S3/042 , H01S3/07 , H01S3/109 , H01S3/1611 , H01S3/1643 , H01S3/1671
摘要： The invention provides a method for making a laser module, comprising: Step 1: fixing a laser crystal and a nonlinear crystal through at least one spacing element to form a first structure; Step 2: assembling the first structure on a substrate; Step 3: removing the spacing element to form a first laser module. According to the invention, the laser crystal and the nonlinear crystal are separately fixed on a heat conductive substrate to form the laser module, thereby the size of the laser module is reduced.
摘要翻译：本发明提供一种制造激光模块的方法，包括：步骤1：通过至少一个间隔元件固定激光晶体和非线性晶体以形成第一结构; 步骤2：在基板上组装第一结构; 步骤3：移除间隔元件以形成第一激光模块。根据本发明，将激光晶体和非线性晶体分别固定在导热基板上以形成激光模块，从而减小激光模块的尺寸。

9. 发明申请

US20130287274A1 Methods and Apparatuses of Unified Capacitive Based Sensing of Touch and Fingerprint 审中-公开
标题翻译：统一电容式触摸和指纹感测方法与装置
公开(公告)号：US20130287274A1
公开(公告)日：2013-10-31
申请号：US13887351
申请日：2013-05-05
申请人： Weidong Shi , Yang Lu
发明人： Weidong Shi , Yang Lu
IPC分类号： G06F3/044 , G06K9/00
CPC分类号： G06F3/044 , G06F2203/0338 , G06K9/00006 , G06K9/0002
摘要： The present invention describes methods and apparatuses for sensing touches and/or fingerprint images with an integrated device comprising, a transparent touch-fingerprint capacitive sensing array comprising a collection of capacitive sensing cells, a multi-resolution scanline driver circuitry, a multi-resolution column driver circuitry, and a readout circuitry coupling with said transparent touch-fingerprint capacitive sensing array wherein said readout circuitry can transmit digital or analog output of selected capacitive sensing cells.
摘要翻译：本发明描述了利用集成设备来感测触摸和/或指纹图像的方法和装置，包括：透明触摸指纹电容感测阵列，其包括电容感测单元的集合，多分辨率扫描线驱动器电路，多分辨率列驱动器电路和与所述透明触摸指纹电容感测阵列耦合的读出电路，其中所述读出电路可以传输所选择的电容感测单元的数字或模拟输出。

10. 发明申请

US20130109143A1 Vertical Gate LDMOS Device 有权
标题翻译：垂直门LDMOS器件
公开(公告)号：US20130109143A1
公开(公告)日：2013-05-02
申请号：US13572281
申请日：2012-08-10
申请人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan , John Xia
发明人： Marco A. Zuniga , Yang Lu , Badredin Fatemizadeh , Jayasimha Prasad , Amit Paul , Jun Ruan , John Xia
IPC分类号： H01L29/78
CPC分类号： H01L29/66704 , H01L21/265 , H01L21/28105 , H01L21/823481 , H01L27/088 , H01L29/0626 , H01L29/063 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66696 , H01L29/78 , H01L29/7802 , H01L29/7825 , H01L29/7827 , H01L29/7835
摘要： The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.
摘要翻译：本申请的特征在于在垂直横向扩散的金属氧化物半导体（LDMOS）晶体管中制造栅极区域的方法。在一个方面，一种方法包括在植入在衬底上的n阱区域上沉积掩模层，图案化掩模层以限定区域，以及在该区域中形成第一沟槽，使得第一沟槽的长度从 n阱区域的表面到n阱区域中的第一深度。该方法还包括通过导电材料填充第一沟槽并在该区域上沉积一层氧化物。该方法还包括蚀刻掉氧化物层的至少一部分以暴露导电材料的一部分，从暴露部分去除导电材料以形成第二沟槽，并用氧化物填充第二沟槽以形成非对称栅极的晶体管。

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