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1. 发明申请

US20100038679A1 FINFET WITH LONGITUDINAL STRESS IN A CHANNEL 有权
标题翻译： FINANCE在通道中具有纵向应力
公开(公告)号：US20100038679A1
公开(公告)日：2010-02-18
申请号：US12191425
申请日：2008-08-14
申请人： KEVIN K. CHAN , Qiqing (Christine) Ouyang , Dae-Gyu Park , Xinhui Wang
发明人： KEVIN K. CHAN , Qiqing (Christine) Ouyang , Dae-Gyu Park , Xinhui Wang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7848
摘要： At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.
摘要翻译：在至少一个半导体鳍片的至少一个沟道区域上形成至少一个栅极电介质，栅电极和栅极帽电介质。在栅电极的侧壁上形成栅极间隔物，在栅电极的两侧露出翅片的端部。半导体鳍片的暴露部分被垂直和横向蚀刻，从而减小端部中的至少一个半导体翅片的高度和宽度。绝缘体层的露出部分也可以凹进。晶格不匹配的半导体材料通过选择性外延生长在至少一个半导体鳍片的剩余端部上，并与外部对准至少一个半导体鳍片。晶格不匹配材料沿着形成在至少一个半导体鳍片上的finFET的沟道施加纵向应力。

2. 发明授权

US07872303B2 FinFET with longitudinal stress in a channel 有权
标题翻译： FinFET在通道中具有纵向应力
公开(公告)号：US07872303B2
公开(公告)日：2011-01-18
申请号：US12191425
申请日：2008-08-14
申请人： Kevin K. Chan , Qiqing Christine Ouyang , Dae-Gyu Park , Xinhui Wang
发明人： Kevin K. Chan , Qiqing Christine Ouyang , Dae-Gyu Park , Xinhui Wang
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7848
摘要： At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.
摘要翻译：在至少一个半导体鳍片的至少一个沟道区域上形成至少一个栅极电介质，栅电极和栅极帽电介质。在栅电极的侧壁上形成栅极间隔物，在栅电极的两侧露出翅片的端部。半导体鳍片的暴露部分被垂直和横向蚀刻，从而减小端部中的至少一个半导体翅片的高度和宽度。绝缘体层的露出部分也可以凹进。晶格不匹配的半导体材料通过选择性外延生长在至少一个半导体鳍片的剩余端部上，并与外部对准至少一个半导体鳍片。晶格不匹配材料沿着形成在至少一个半导体鳍片上的finFET的沟道施加纵向应力。

3. 发明授权

US09287136B2 FinFET field-effect transistors with atomic layer doping 有权
标题翻译：具有原子层掺杂的FinFET场效应晶体管
公开(公告)号：US09287136B2
公开(公告)日：2016-03-15
申请号：US13606873
申请日：2012-09-07
申请人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
发明人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
IPC分类号： H01L29/78 , H01L27/088 , H01L21/20 , H01L21/24 , H01L21/314 , H01L21/02 , H01L29/36 , H01L21/225 , H01L29/66 , H01L29/165
CPC分类号： H01L21/31 , H01L21/0228 , H01L21/2254 , H01L29/165 , H01L29/365 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
摘要翻译：公开了使用原子层掺杂工艺制造的场效应晶体管。根据原子层掺杂方法的实施方案，制备半导体表面和掺杂剂气体混合物。此外，通过在小于500托的压力和300℃至750℃的温度下将掺杂剂气体混合物施加到半导体表面，在半导体表面上生长掺杂剂层。掺杂剂层包括在与半导体表面上的原子反应的每立方厘米的最小4×10 20有源掺杂剂原子使得反应的原子增加了半导体表面的导电性。

4. 发明申请

US20130032883A1 FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING 有权
公开(公告)号：US20130032883A1
公开(公告)日：2013-02-07
申请号：US13198255
申请日：2011-08-04
申请人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
发明人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
IPC分类号： H01L29/78 , H01L21/336 , H01L21/24
CPC分类号： H01L21/31 , H01L21/0228 , H01L21/2254 , H01L29/165 , H01L29/365 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.

5. 发明申请

US20110062518A1 finFETS AND METHODS OF MAKING SAME 有权
公开(公告)号：US20110062518A1
公开(公告)日：2011-03-17
申请号：US12561606
申请日：2009-09-17
申请人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
发明人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

6. 发明授权

US09048261B2 Fabrication of field-effect transistors with atomic layer doping 有权
标题翻译：用原子层掺杂制造场效晶体管
公开(公告)号：US09048261B2
公开(公告)日：2015-06-02
申请号：US13198255
申请日：2011-08-04
申请人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
发明人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
IPC分类号： H01L21/44 , H01L21/441 , H01L29/66 , H01L21/225 , H01L29/78 , H01L29/165
CPC分类号： H01L21/31 , H01L21/0228 , H01L21/2254 , H01L29/165 , H01L29/365 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
摘要翻译：公开了使用原子层掺杂工艺制造的场效应晶体管。根据原子层掺杂方法的实施方案，制备半导体表面和掺杂剂气体混合物。此外，通过在小于500托的压力和300℃至750℃的温度下将掺杂剂气体混合物施加到半导体表面，在半导体表面上生长掺杂剂层。掺杂剂层包括在与半导体表面上的原子反应的每立方厘米的最小4×10 20有源掺杂剂原子使得反应的原子增加了半导体表面的导电性。

7. 发明授权

US08410544B2 finFETs and methods of making same 有权
标题翻译： finFET及其制造方法
公开(公告)号：US08410544B2
公开(公告)日：2013-04-02
申请号：US13228519
申请日：2011-09-09
申请人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
发明人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.
摘要翻译：一种合并多鳍鳍鳍鳍片的制造方法和结构。该方法包括从具有非常薄的掩埋氧化物层的SOI衬底的硅层形成单晶硅散热片，并通过从衬底生长垂直外延硅并从散热片的端部生成水平外延硅，从而将翅片的端部区域合并垂直外延硅生长占优势。

8. 发明申请

US20130032865A1 FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING 有权
公开(公告)号：US20130032865A1
公开(公告)日：2013-02-07
申请号：US13606873
申请日：2012-09-07
申请人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
发明人： Kevin K. Chan , Young-Hee Kim , Isaac Lauer , Ramachandran Muralidhar , Dae-Gyu Park , Xinhui Wang , Min Yang
IPC分类号： H01L29/78
CPC分类号： H01L21/31 , H01L21/0228 , H01L21/2254 , H01L29/165 , H01L29/365 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/66803 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.

9. 发明申请

US20110316081A1 finFETS AND METHODS OF MAKING SAME 有权
标题翻译：鳍片及其制造方法
公开(公告)号：US20110316081A1
公开(公告)日：2011-12-29
申请号：US13228519
申请日：2011-09-09
申请人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
发明人： Kevin K. Chan , Thomas Safron Kanarsky , Jinghong Li , Christine Qiqing Ouyang , Dae-Gyu Park , Zhibin Ren , Xinhui Wang , Haizhou Yin
IPC分类号： H01L27/12
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.
摘要翻译：一种合并多鳍鳍鳍鳍片的制造方法和结构。该方法包括从具有非常薄的掩埋氧化物层的SOI衬底的硅层形成单晶硅散热片，并通过从衬底生长垂直外延硅并从散热片的端部生成水平外延硅，从而将翅片的端部区域合并垂直外延硅生长占优势。

10. 发明授权

US09105741B2 Method of replacement source/drain for 3D CMOS transistors 有权
标题翻译： 3D CMOS晶体管替代源极/漏极的方法
公开(公告)号：US09105741B2
公开(公告)日：2015-08-11
申请号：US13614062
申请日：2012-09-13
申请人： Kevin K. Chan , Jinghong Li , Dae-Gyu Park , Xinhui Wang , Yun-Yu Wang , Qingyun Yang
发明人： Kevin K. Chan , Jinghong Li , Dae-Gyu Park , Xinhui Wang , Yun-Yu Wang , Qingyun Yang
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L21/84 , H01L29/78 , H01L27/12
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/7848
摘要： A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.
摘要翻译：形成半导体结构的方法可以包括形成至少一个翅片并且在所述至少一个翅片结构的第一部分上形成栅极。栅极间隔物可以形成在栅极的侧壁上，由此间隔物的形成产生与该至少一个鳍片的侧壁相邻的凹陷区域。形成第一外延区域，其覆盖所述凹陷区域中的一个和所述至少一个翅片的第二部分，使得所述第二部分从所述栅极间隔物之一向外延伸。通过蚀刻第一外延区域和至少一个鳍片的第二部分，在一个凹陷区域内形成第一外延层。第二外延区域形成在相邻一个间隔物的位置和在一个凹陷区域内的第一外延层上方。

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