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1. 发明授权

US07902012B2 High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof 有权
标题翻译：通过二维带隙工程实现的高速横向异质结MISFET及其方法
公开(公告)号：US07902012B2
公开(公告)日：2011-03-08
申请号：US12534562
申请日：2009-08-03
申请人： Qiqing Christine Ouyang , Jack Oon Chu
发明人： Qiqing Christine Ouyang , Jack Oon Chu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/802 , Y10S438/933
摘要： A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.
摘要翻译：描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变横向沟道结构的方法，其在单晶半导体衬底上结合了漏极，主体和源极区域，其中在晶体管的源极和主体，其中源极区域和沟道独立地相对于身体区域进行晶格应变。本发明通过异质结和晶格应变来减少来自源极区的漏电流的问题，同时通过选择半导体材料和合金组成独立地允许沟道区域中的晶格应变以增加迁移率。

2. 发明申请

US20100038679A1 FINFET WITH LONGITUDINAL STRESS IN A CHANNEL 有权
标题翻译： FINANCE在通道中具有纵向应力
公开(公告)号：US20100038679A1
公开(公告)日：2010-02-18
申请号：US12191425
申请日：2008-08-14
申请人： KEVIN K. CHAN , Qiqing (Christine) Ouyang , Dae-Gyu Park , Xinhui Wang
发明人： KEVIN K. CHAN , Qiqing (Christine) Ouyang , Dae-Gyu Park , Xinhui Wang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7848
摘要： At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.
摘要翻译：在至少一个半导体鳍片的至少一个沟道区域上形成至少一个栅极电介质，栅电极和栅极帽电介质。在栅电极的侧壁上形成栅极间隔物，在栅电极的两侧露出翅片的端部。半导体鳍片的暴露部分被垂直和横向蚀刻，从而减小端部中的至少一个半导体翅片的高度和宽度。绝缘体层的露出部分也可以凹进。晶格不匹配的半导体材料通过选择性外延生长在至少一个半导体鳍片的剩余端部上，并与外部对准至少一个半导体鳍片。晶格不匹配材料沿着形成在至少一个半导体鳍片上的finFET的沟道施加纵向应力。

3. 发明授权

US07525161B2 Strained MOS devices using source/drain epitaxy 有权
标题翻译：使用源极/漏极外延的应变MOS器件
公开(公告)号：US07525161B2
公开(公告)日：2009-04-28
申请号：US11669902
申请日：2007-01-31
申请人： Meikei Ieong , Xiao Hu Liu , Qiqing Christine Ouyang , Siddhartha Panda , Haizhou Yin
发明人： Meikei Ieong , Xiao Hu Liu , Qiqing Christine Ouyang , Siddhartha Panda , Haizhou Yin
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848 , H01L29/78687
摘要： NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.
摘要翻译：公开了具有单独应变通道区域的NMOS和PMOS器件结构及其制造方法。 NMOS器件的源极和漏极由引起NMOS器件沟道在拉伸方向上的应变移动的材料外延生长。而PMOS器件的源极和漏极是外延生长的，这种材料导致PMOS器件沟道在压缩方向上的应变移动。

4. 发明授权

US07057216B2 High mobility heterojunction complementary field effect transistors and methods thereof 有权
标题翻译：高迁移率异质结互补场效应晶体管及其方法
公开(公告)号：US07057216B2
公开(公告)日：2006-06-06
申请号：US10698122
申请日：2003-10-31
申请人： Qiqing Christine Ouyang , Xiangdong Chen
发明人： Qiqing Christine Ouyang , Xiangdong Chen
IPC分类号： H01L29/778
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/7841
摘要： In all representative embodiments presented, the Ge concentration in the source and drain 10 and the SiGe epitaxial channel layer 20 is in the 15% to 50% range, preferably between about 20% to 40%. The SiGe thicknesses in the source/drain 10 are staying below the critical thickness for the given Ge concentration. The critical thickness is defined such that above it the SiGe will relax and defects and dislocations will form. The thickness of the SiGe epitaxial layer 20 typically is between about 5nm and 15nm. The thickness of the epitaxial Si layer 30 is typically between about 5nm and 15nm. FIG. 1A shows an embodiment where the body is bulk Si. These type of devices are the most common devices in present day microelectronics. FIGS. 1B and 1C show representative embodiment of the heterojunction source/drain FET device when the Si body 40 is disposed on top of an insulating material 55. This type of technology is commonly referred to as silicon on insulator (SOI) technology. The insulator material 55 usually, and preferably, is SiO2. FIG. 1B shows an SOI embodiment where the body 40 has enough volume to contain mobile charges. Such SOI devices are called partially depleted devices. FIG. 1C shows an SOI embodiment where the volume of the body 40 is insufficient to contain mobile charges. Such SOI devices are called fully depleted devices. For devices shown in FIG. 1B and 1C there is, at least a thin, layer of body underneath the source and drain 10. This body material serves as the seed material onto which the epitaxial SiGe source and drain 10 are grown. In an alternate embodiment, shown in FIG. 1D. for extremely thin fully depleted SOI devices, one could grow the source and drain 10 laterally, from a lateral seeding, in which case the source and drain 10 would penetrate all the way down to the insulating layer 55.
摘要翻译：公开了一种用于高性能场效应装置的结构和制造方法。 MOS结构包括一个导电类型的晶体Si体，在作为空穴的掩埋沟道的Si体上外延生长的外延生长的SiGe层，在用作电子的表面通道的SiGe层上外延生长的Si层，以及漏极含有与Si体相反的导电类型的外延沉积的应变SiGe。 SiGe源极/漏极与Si体形成异质结和冶金结，它们彼此重合，其公差小于约10nm，优选小于约5nm。异质结构源/漏极有助于减少短沟道效应。由于在压缩应变的SiGe沟道中增加的空穴迁移率，这些结构对于PMOS是特别有利的。代表性的实施例包括大块和SOI上的CMOS结构。

5. 发明授权

US06943407B2 Low leakage heterojunction vertical transistors and high performance devices thereof 失效
标题翻译：低漏极异质结垂直晶体管及其高性能器件
公开(公告)号：US06943407B2
公开(公告)日：2005-09-13
申请号：US10463039
申请日：2003-06-17
申请人： Qiqing Christine Ouyang , Jack Oon Chu
发明人： Qiqing Christine Ouyang , Jack Oon Chu
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L29/12 , H01L29/78 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/778 , H01L21/823807 , H01L21/823885 , H01L29/045 , H01L29/161 , H01L29/165 , H01L29/7781 , H01L29/7782 , H01L29/7789 , H01L29/7828
摘要： A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.
摘要翻译：描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的垂直沟道结构的方法，其在垂直单晶半导体结构的侧壁上结合有漏极，主体和源极区域，其中异质结为形成在晶体管的源极和主体之间，其中源极区域和沟道独立地相对于体区域进行晶格应变，并且其中漏极区域包含碳掺杂区域以防止掺杂剂（即，B和P）扩散到身体。本发明减少了短沟道效应的问题，例如漏极引起的栅极降低和从源极到漏极区域的漏电流经由异质结，并且同时独立地允许沟道区域中的晶格应变，以通过选择半导体材料增加迁移率。栅极长度低于100nm的可扩展性的问题通过源极和体区之间的异质结来克服。

6. 发明授权

US07453113B2 Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof 失效
标题翻译：超可伸缩高速异质结垂直n沟道MISFET及其方法
公开(公告)号：US07453113B2
公开(公告)日：2008-11-18
申请号：US11735711
申请日：2007-04-16
申请人： Qiqing Christine Ouyang , Jack Oon Chu
发明人： Qiqing Christine Ouyang , Jack Oon Chu
IPC分类号： H01L27/108
CPC分类号： H01L29/7781 , H01L29/161 , H01L29/165 , H01L29/778 , H01L29/7782 , H01L29/7789 , H01L29/7828 , H01L29/78642 , H01L29/78687
摘要： A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.
摘要翻译：描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变垂直沟道的方法，其中在垂直单晶半导体结构的侧壁上结合有漏极，主体和源极区域，其中异质结形成在晶体管的源极和主体之间，其中源极区域和沟道相对于主体区域独立地晶格应变，并且其中漏极区域包含碳掺杂区域以防止掺杂剂（硼）扩散到体内。本发明通过异质结和晶格应变来减少来自源极区域的漏电流的问题，同时通过选择半导体材料独立地允许沟道区域中的晶格应变以增加迁移率。

7. 发明授权

US07205604B2 Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof 有权
标题翻译：超可伸缩高速异质结垂直n沟道MISFET及其方法
公开(公告)号：US07205604B2
公开(公告)日：2007-04-17
申请号：US10463038
申请日：2003-06-17
申请人： Qiqing Christine Ouyang , Jack Oon Chu
发明人： Qiqing Christine Ouyang , Jack Oon Chu
IPC分类号： H01L29/94
CPC分类号： H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7789 , H01L29/7828
摘要： A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a heterojunction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the heterojunction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.
摘要翻译：描述了形成场效应晶体管，场效应晶体管和CMOS电路的应变垂直沟道的方法，其中在垂直单晶半导体结构的侧壁上结合有漏极，主体和源极区域，其中形成异质结在晶体管的源极和主体之间，其中源极区域和沟道相对于体区域独立地晶格应变，并且其中漏极区域包含碳掺杂区域以防止掺杂剂（硼）扩散到体内。本发明通过异质结和晶格应变来减少来自源区的漏电流的问题，同时通过选择半导体材料独立地允许沟道区中的晶格应变以增加迁移率。

8. 发明申请

US20120092771A1 EMBEDDED VERTICAL OPTICAL GRATING FOR HETEROGENEOUS INTEGRATION 有权
标题翻译：嵌入式垂直光栅用于异构整合
公开(公告)号：US20120092771A1
公开(公告)日：2012-04-19
申请号：US12906697
申请日：2010-10-18
申请人： Fei Liu , Qiqing (Christine) Ouyang , Keith Kwong Hon Wong
发明人： Fei Liu , Qiqing (Christine) Ouyang , Keith Kwong Hon Wong
IPC分类号： G02B5/18 , H01L21/30
CPC分类号： G02B5/18 , G02B5/1857 , G02B5/1866 , G02B6/124 , G02B2006/12107 , G03F7/2016 , H01L21/30
摘要： An embedded vertical optical grating, a semiconductor device including the embedded vertical optical grating and a method for forming the same. The method for forming the embedded optical grating within a substrate includes depositing a hard mask layer on the substrate, patterning at least one opening within the hard mask layer, vertically etching a plurality of scallops within the substrate corresponding to the at least one opening within the hard mask layer, removing the hard mask layer, and forming an oxide layer within the plurality of scallops to form the embedded vertical optical grating.
摘要翻译：嵌入式垂直光栅，包括嵌入式垂直光栅的半导体器件及其形成方法。用于在衬底内形成嵌入式光栅的方法包括在衬底上沉积硬掩模层，图案化硬掩模层内的至少一个开口，垂直蚀刻衬底内对应于在该掩模层内的至少一个开口的多个扇贝硬掩模层，去除硬掩模层，以及在多个扇贝内形成氧化物层以形成嵌入的垂直光栅。

9. 发明申请

US20100159658A1 HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL BANDGAP ENGINEERING AND METHODS THEREOF 有权
标题翻译：通过二维带隙工程实现的高速横向异相MISFET及其方法
公开(公告)号：US20100159658A1
公开(公告)日：2010-06-24
申请号：US12534562
申请日：2009-08-03
申请人： Qiqing Christine Ouyang , Jack Oon Chu
发明人： Qiqing Christine Ouyang , Jack Oon Chu
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/802 , Y10S438/933
摘要： A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.
摘要翻译：描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变横向沟道结构的方法，其在单晶半导体衬底上结合了漏极，主体和源极区域，其中在晶体管的源极和主体，其中源极区域和沟道独立地相对于身体区域进行晶格应变。本发明通过异质结和晶格应变来减少来自源极区的漏电流的问题，同时通过选择半导体材料和合金组成独立地允许沟道区域中的晶格应变以增加迁移率。

10. 发明授权

US07872303B2 FinFET with longitudinal stress in a channel 有权
标题翻译： FinFET在通道中具有纵向应力
公开(公告)号：US07872303B2
公开(公告)日：2011-01-18
申请号：US12191425
申请日：2008-08-14
申请人： Kevin K. Chan , Qiqing Christine Ouyang , Dae-Gyu Park , Xinhui Wang
发明人： Kevin K. Chan , Qiqing Christine Ouyang , Dae-Gyu Park , Xinhui Wang
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7848
摘要： At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.
摘要翻译：在至少一个半导体鳍片的至少一个沟道区域上形成至少一个栅极电介质，栅电极和栅极帽电介质。在栅电极的侧壁上形成栅极间隔物，在栅电极的两侧露出翅片的端部。半导体鳍片的暴露部分被垂直和横向蚀刻，从而减小端部中的至少一个半导体翅片的高度和宽度。绝缘体层的露出部分也可以凹进。晶格不匹配的半导体材料通过选择性外延生长在至少一个半导体鳍片的剩余端部上，并与外部对准至少一个半导体鳍片。晶格不匹配材料沿着形成在至少一个半导体鳍片上的finFET的沟道施加纵向应力。

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