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1. 发明授权

US08319594B2 Ceramic electronic component 有权
标题翻译：陶瓷电子元件
公开(公告)号：US08319594B2
公开(公告)日：2012-11-27
申请号：US13354369
申请日：2012-01-20
申请人： Koji Sato , Yukio Sanada , Makoto Ogawa , Yasuhiro Nishisaka
发明人： Koji Sato , Yukio Sanada , Makoto Ogawa , Yasuhiro Nishisaka
IPC分类号： H01F5/00
CPC分类号： H01G4/232 , H01G4/2325 , H01G4/30
摘要： A ceramic electronic component includes a ceramic body, a first external electrode, and a second external electrode. The first and second external electrodes are disposed on a principal surface, which is directed to the mounting surface side, of the ceramic body so as to face each other with a predetermined gap region therebetween. The external electrodes each include a base layer and a Cu plating layer which covers the base layer. In each of the first and second external electrodes, an expression 0.1≦t/d≦0.5 is satisfied, where t is a thickness of the Cu plating layer at an end of the base layer on a gap region side, and d is a distance from the end of the base layer on the gap region side to an end of the Cu plating layer on the gap region side.
摘要翻译：陶瓷电子部件包括陶瓷体，第一外部电极和第二外部电极。第一外部电极和第二外部电极被设置在陶瓷体的朝向安装面侧的主面上，以便在它们之间以预定的间隙区域彼此面对。外部电极各自包括基层和覆盖基层的Cu镀层。在第一外部电极和第二外部电极中的每一个中，满足表达式0.1＆nlE; t / d＆nlE; 0.5，其中t是在间隙区域侧的基底层的端部处的Cu镀层的厚度，d是从间隙区域侧的基底层的端部到间隙区域侧的Cu镀层的端部的距离。

2. 发明授权

US08797711B2 Electronic component and producing method thereof 有权
标题翻译：电子元件及其制造方法
公开(公告)号：US08797711B2
公开(公告)日：2014-08-05
申请号：US12632823
申请日：2009-12-08
申请人： Seiichi Matsumoto , Toshiyuki Iwanaga , Makoto Ogawa , Akihiro Motoki
发明人： Seiichi Matsumoto , Toshiyuki Iwanaga , Makoto Ogawa , Akihiro Motoki
IPC分类号： H01G4/228
CPC分类号： H01G4/30 , H01G4/232
摘要： A region where a plating film constituting an external electrode is formed can be accurately controlled in an electronic component in which the external electrode is formed by directly plating a particular region in a surface of a component body. In a component body, a bump is provided in a position in which a region where an external electrode should be formed is partitioned. In a plating process, growth of the plating film constituting the external electrode is substantially stopped or delayed in the bump. As a result, a termination point of the growth of the plating film constituting the external electrode can be accurately controlled in the position of the bump.
摘要翻译：在形成外部电极的电子部件中，通过直接对构成体的表面的特定区域进行电镀，能够精确地控制形成有构成外部电极的镀膜的区域。在构成体中，在形成有外部电极的区域被分隔的位置设置凸块。在电镀工艺中，构成外部电极的镀膜的生长在凸块中基本上停止或延迟。结果，可以在凸块的位置上精确地控制构成外部电极的镀膜的生长终止点。

3. 发明授权

US08730646B2 Laminated electronic component and method for manufacturing the same 有权
标题翻译：层压电子部件及其制造方法
公开(公告)号：US08730646B2
公开(公告)日：2014-05-20
申请号：US12466435
申请日：2009-05-15
申请人： Kenichi Kawasaki , Shunsuke Takeuchi , Akihiro Motoki , Makoto Ogawa , Toshiyuki Iwanaga
发明人： Kenichi Kawasaki , Shunsuke Takeuchi , Akihiro Motoki , Makoto Ogawa , Toshiyuki Iwanaga
IPC分类号： H01G4/008 , H01G2/20 , H01G4/228
CPC分类号： H01G4/005 , H01G4/008 , H01G4/232
摘要： A laminated electronic component includes outer terminal electrodes including lower plating films including metal particles having an average size of 0.5 μm or less, the lower plating films being formed by directly plating an outer surface of an electronic component body such that the lower plating films are electrically connected to exposed portions of inner conductors. The outer terminal electrodes may further include upper plating films formed on the lower plating films, the upper plating films being defined by one or more layers. Metal particles defining the upper plating films may have an average size of 0.5 μm or less. The metal particles defining the lower plating films may be Cu particles.
摘要翻译：层叠电子部件包括外部端子电极，其包括具有平均尺寸为0.5μm以下的金属粒子的下部电镀膜，下部电镀膜通过直接电镀电子部件主体的外表面而形成，使得下部电镀膜为电气连接到内部导体的暴露部分。外部端子电极还可以包括形成在下部镀膜上的上部镀膜，上部镀膜由一层或多层限定。限定上镀膜的金属粒子的平均粒径可以为0.5μm以下。限定下镀层的金属颗粒可以是Cu颗粒。

4. 发明授权

US08411409B2 Ceramic electronic component and manufacturing method therefor 有权
标题翻译：陶瓷电子元件及其制造方法
公开(公告)号：US08411409B2
公开(公告)日：2013-04-02
申请号：US13161535
申请日：2011-06-16
申请人： Makoto Ogawa , Akihiro Motoki , Masahito Saruban , Toshiyuki Iwanaga , Syunsuke Takeuchi , Kiyoyasu Sakurada
发明人： Makoto Ogawa , Akihiro Motoki , Masahito Saruban , Toshiyuki Iwanaga , Syunsuke Takeuchi , Kiyoyasu Sakurada
IPC分类号： H01G4/30
CPC分类号： H01G4/12 , H01C1/14 , H01G4/005 , H01G4/232
摘要： When an external terminal electrode of a ceramic electronic component such as a laminated ceramic capacitor is formed by plating, plating growth may be also caused even in an undesired location. The ceramic surface provided by a component main body is configured to include a high plating growth region of, for example, a barium titanate based ceramic, which exhibits relatively high plating growth, and a low plating growth region of, for example, a calcium zirconate based ceramic, which exhibits relatively low plating growth. The plating film constituting a first layer to define a base for an external terminal electrode is formed in such a way that the growth of a plated deposit deposited with conductive surfaces provided by exposed ends of internal electrodes as starting points is limited so as not to cross over a boundary between the high plating growth region and the low plating growth region toward the low plating growth region.
摘要翻译：当通过电镀形成层压陶瓷电容器等陶瓷电子部件的外部端子电极时，即使在不希望的位置也可能产生电镀生长。由组件主体提供的陶瓷表面被构造为包括例如呈现较高镀层生长的例如钛酸钡系陶瓷的高镀层生长区域和例如锆酸锆的低镀层生长区域其具有相对较低的电镀生长。构成用于限定外部端子电极的基底的第一层的电镀膜以这样的方式形成，使得以由内部电极的暴露端作为起点设置的导电表面沉积的镀覆沉积物的生长被限制为不交叉在高电镀生长区域和低电镀生长区域之间的边界朝向低电镀生长区域。

5. 发明授权

US08154848B2 Multilayer ceramic electronic component including external electrodes that include a plating layer having a low film stress 有权
标题翻译：包括具有低膜应力的镀层的外部电极的多层陶瓷电子部件
公开(公告)号：US08154848B2
公开(公告)日：2012-04-10
申请号：US12354026
申请日：2009-01-15
申请人： Akihiro Motoki , Makoto Ogawa , Shunsuke Takeuchi , Kenichi Kawasaki
发明人： Akihiro Motoki , Makoto Ogawa , Shunsuke Takeuchi , Kenichi Kawasaki
IPC分类号： H01G4/228 , H01G4/06
CPC分类号： H01G4/005 , H01G4/008 , H01G4/12 , H01G4/30
摘要： A multilayer ceramic electronic component includes a laminate including a stack of a plurality of ceramic layers and a plurality of internal electrodes extending along interfaces between the ceramic layers, and a plurality of external electrodes electrically connecting the internal electrodes exposed at surfaces of the laminate. Each external electrode includes a plating layer at least at the portion directly connected to the internal electrodes. The plating layer has a compressive film stress of about 100 MPa or less or a tensile film stress of about 100 MPa or less.
摘要翻译：多层陶瓷电子部件包括层叠体，其包括多个陶瓷层的叠层和沿着陶瓷层之间的界面延伸的多个内部电极，以及电连接在层叠体的表面露出的内部电极的多个外部电极。每个外部电极至少包括直接连接到内部电极的部分的镀层。镀层的压缩应力为约100MPa以下或拉伸膜应力为约100MPa以下。

6. 发明授权

US08018359B2 Conversion of bit lengths into codes 失效
标题翻译：将位长转换为代码
公开(公告)号：US08018359B2
公开(公告)日：2011-09-13
申请号：US12753784
申请日：2010-04-02
申请人： Makoto Ogawa , Tadayuki Okada , Kiyoshi Takemura , Nobuyoshi Tanaka
发明人： Makoto Ogawa , Tadayuki Okada , Kiyoshi Takemura , Nobuyoshi Tanaka
IPC分类号： H03M7/46
CPC分类号： H03M7/42
摘要： Various embodiments are provided to reduce a processing time taken when plural bit lengths each assigned to plural strings are converted into plural codes. In one exemplary embodiment, in response to input of the plurality of bit lengths, a number of strings assigned each of the bit lengths, a bit length assigned to each of the strings, and a sequence number of each string in a group of strings assigned each of the bit lengths are recorded. A plurality of base codes are generated on the basis of the numbers of the strings recorded by the recording unit, the base codes each being a code used as a base for codes having the same one of the bit lengths. A plurality of codes is generated by performing in parallel a plurality of processes respectively for the plurality of strings.
摘要翻译：提供了各种实施例，以减少每个分配给多个字符串的多个位长度被转换成多个代码所需的处理时间。在一个示例性实施例中，响应于多个比特长度的输入，分配每个比特长度的字符串的数量，分配给每个字符串的比特长度以及被分配的一组字符串中的每个字符串的序列号记录每个位长度。基于由记录单元记录的串的数量生成多个基本码，每个基准码是用作具有相同比特长度的码的基础的码。通过分别并行地执行多个字符串来生成多个代码。

7. 发明授权

US07764484B2 Multilayer electronic component and method for manufacturing the same 有权
标题翻译：多层电子元件及其制造方法
公开(公告)号：US07764484B2
公开(公告)日：2010-07-27
申请号：US12142924
申请日：2008-06-20
申请人： Akihiro Motoki , Makoto Ogawa , Kenichi Kawasaki , Shunsuke Takeuchi
发明人： Akihiro Motoki , Makoto Ogawa , Kenichi Kawasaki , Shunsuke Takeuchi
IPC分类号： H01G4/00
CPC分类号： H01G4/30 , H01G4/232 , H01G4/2325 , H05K1/0306 , H05K1/092 , H05K3/102 , H05K3/246 , H05K3/403 , H05K2201/0347 , H05K2203/025 , Y10T29/417 , Y10T29/43 , Y10T29/435 , Y10T428/25
摘要： A method for manufacturing a multilayer electronic component includes a step of preparing a laminate which includes a plurality of stacked insulator layers and a plurality of internal electrodes extending along the interfaces between the insulator layers, and in which an end of each of the plurality of internal electrodes is exposed at a predetermined surface corresponding to one of the first and second end surfaces; a step of forming external electrodes on the predetermined surfaces; and a step of forming thick-film edge electrodes at edge portions. The step of forming external electrodes includes a step of attaching a plurality of conductive particles having a particle size of about 1 μm or more to the predetermined surfaces of the laminate, and a step of performing plating directly on the predetermined surfaces to which the conductive particles are attached.
摘要翻译：一种制造多层电子部件的方法包括制备层压体的步骤，该层压体包括多个堆叠的绝缘体层和沿着绝缘体层之间的界面延伸的多个内部电极，并且其中多个内部电极在对应于第一和第二端面之一的预定表面处露出; 在所述预定表面上形成外部电极的步骤; 以及在边缘部分形成厚膜边缘电极的步骤。形成外部电极的步骤包括将多个具有约1μm以上的粒径的导电粒子附着在层叠体的规定表面上的步骤，以及在导电粒子的规定表面上直接进行电镀的工序附上。

8. 发明授权

US07589952B2 Multilayer electronic device and method for manufacturing the same 有权
标题翻译：多层电子器件及其制造方法
公开(公告)号：US07589952B2
公开(公告)日：2009-09-15
申请号：US12109371
申请日：2008-04-25
申请人： Akihiro Motoki , Kenichi Kawasaki , Makoto Ogawa , Shigeyuki Kuroda , Tatsuo Kunishi
发明人： Akihiro Motoki , Kenichi Kawasaki , Makoto Ogawa , Shigeyuki Kuroda , Tatsuo Kunishi
IPC分类号： H01G4/228
CPC分类号： H01G4/2325 , H01G4/30 , Y10T29/435
摘要： A multilayer electronic device includes a laminate and an external electrode that is formed on an end surface of the laminate after a plurality of conductive particles having a particle diameter of about 1 μm or more is adhered to the end surface of the laminate, for example, by a sandblast method or a brush polishing method. The external electrode is defined by a plating film that is formed by electroplating or electroless plating.
摘要翻译：例如，多层电子器件包括层压体和形成在层叠体的端面上的外部电极，该多个电子器件在层叠体的端面附着有多个粒径为1μm以上的导电粒子之后，通过喷砂法或刷子抛光法。外部电极由通过电镀或无电镀形成的电镀膜限定。

9. 发明授权

US07481305B2 Lock-up mechanism for torque converter 失效
标题翻译：变矩器锁定机构
公开(公告)号：US07481305B2
公开(公告)日：2009-01-27
申请号：US11186867
申请日：2005-07-22
申请人： Hiroyuki Sakai , Makoto Ogawa , Takamitsu Kuroyanagi , Osamu Yoshida , Eiji Hayashi , Hideki Ogawa , Tamotsu Fujii , Kenji Maruo , Hideaki Takabayashi
发明人： Hiroyuki Sakai , Makoto Ogawa , Takamitsu Kuroyanagi , Osamu Yoshida , Eiji Hayashi , Hideki Ogawa , Tamotsu Fujii , Kenji Maruo , Hideaki Takabayashi
IPC分类号： F16H45/02 , F16D13/74
CPC分类号： F16D13/64 , F16H45/02 , F16H2045/0226 , F16H2045/0289 , F16H2045/0294
摘要： A lock-up mechanism for a torque converter comprising a lock-up clutch secured thereto with a friction liner having a friction surface, and a front cover having an engaging surface adapted to be engaged with the friction surface, is wherein either the friction surface or the engaging surface is formed therein with a substantially annular circumferential groove.
摘要翻译：一种用于扭矩转换器的锁定机构，其包括固定到其上的具有摩擦表面的摩擦衬垫的锁止离合器和具有适于与摩擦表面接合的接合表面的前盖，其中摩擦表面或接合表面形成有大致环形的周向槽。

10. 发明授权

US07382171B2 Semiconductor circuit for detecting a signal propagation time 有权
标题翻译：用于检测信号传播时间的半导体电路
公开(公告)号：US07382171B2
公开(公告)日：2008-06-03
申请号：US10779802
申请日：2004-02-18
申请人： Makoto Ogawa , Tadashi Shibata
发明人： Makoto Ogawa , Tadashi Shibata
IPC分类号： H03H11/26
CPC分类号： H03K5/13 , G06K9/62
摘要： There is provided a semiconductor circuit including three or more nodes at least including one input node and one output node, plural paths which are connected between the three or more nodes and whose signal propagation directions between the nodes are regulated, a signal propagation time regulator for regulating a signal propagation time of each of the paths, an input unit for inputting a predetermined input signal to the input node, and a detector for detecting a time required for the input signal to propagate through the paths and arrive at the output node.
摘要翻译：提供了包括三个或更多个节点的半导体电路，至少包括一个输入节点和一个输出节点，连接在三个或更多个节点之间的多个路径，并且其节点之间的信号传播方向被调节，信号传播时间调节器调节每个路径的信号传播时间，用于向输入节点输入预定输入信号的输入单元，以及检测器，用于检测输入信号通过路径传播并到达输出节点所需的时间。

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