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1. 发明申请

US20120117354A1 STORAGE DEVICE IN WHICH FORWARDING-FUNCTION-EQUIPPED MEMORY NODES ARE MUTUALLY CONNECTED AND DATA PROCESSING METHOD 有权
标题翻译：存储设备，其中前向功能的存储器端口被连接和数据处理方法
公开(公告)号：US20120117354A1
公开(公告)日：2012-05-10
申请号：US13293399
申请日：2011-11-10
申请人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
发明人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
IPC分类号： G06F12/02
CPC分类号： H04L49/253 , G06F3/0605 , G06F3/0635 , G06F3/0656 , G06F3/0658 , G06F3/0683 , H04L12/6418 , H04L45/74
摘要： According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
摘要翻译：根据一个实施例，存储设备包括多个存储器节点。每个存储器节点包括多个输入端口，多个输出端口，选择器，分组控制器和存储器。选择器将输入到输入端口的数据包输出输出到其中一个输出端口。分组控制器控制选择器。内存存储数据。存储器节点在输入端口和输出端口相互连接。存储器节点具有由其物理位置确定的地址。当接收到没有寻址到具有分组控制器的存储器节点的分组时，分组控制器基于包括分组的目的地地址的信息和具有分组控制器的存储器节点的地址来切换输出分组的输出端口。

2. 发明授权

US09246709B2 Storage device in which forwarding-function-equipped memory nodes are mutually connected and data processing method 有权
标题翻译：具有转发功能的存储器节点相互连接的存储设备和数据处理方法
公开(公告)号：US09246709B2
公开(公告)日：2016-01-26
申请号：US13293399
申请日：2011-11-10
申请人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
发明人： Kosuke Tatsumura , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki , Yoshifumi Nishi , Takao Marukame , Takahiro Kurita
IPC分类号： G06F12/02 , H04L12/64 , G06F3/06
CPC分类号： H04L49/253 , G06F3/0605 , G06F3/0635 , G06F3/0656 , G06F3/0658 , G06F3/0683 , H04L12/6418 , H04L45/74
摘要： According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
摘要翻译：根据一个实施例，存储设备包括多个存储器节点。每个存储器节点包括多个输入端口，多个输出端口，选择器，分组控制器和存储器。选择器将输入到输入端口的数据包输出输出到其中一个输出端口。分组控制器控制选择器。内存存储数据。存储器节点在输入端口和输出端口相互连接。存储器节点具有由其物理位置确定的地址。当接收到没有寻址到具有分组控制器的存储器节点的分组时，分组控制器基于包括分组的目的地地址的信息和具有分组控制器的存储器节点的地址来切换输出分组的输出端口。

3. 发明授权

US09007823B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09007823B2
公开(公告)日：2015-04-14
申请号：US13480853
申请日：2012-05-25
申请人： Takahiro Kurita , Yoshifumi Nishi , Kosuke Tatsumura , Atsuhiro Kinoshita
发明人： Takahiro Kurita , Yoshifumi Nishi , Kosuke Tatsumura , Atsuhiro Kinoshita
IPC分类号： G11C11/34 , H01L21/28 , G11C7/02 , G11C11/403 , H01L29/423 , H01L29/51 , H01L27/108
CPC分类号： H01L21/28291 , G11C7/02 , G11C11/403 , H01L21/28282 , H01L27/108 , H01L27/10873 , H01L29/4234 , H01L29/516
摘要： A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.
摘要翻译：根据实施例的半导体器件包括：第一晶体管，包括连接到第一互连的栅极，第一源极和第一漏极，第一源极和第一漏极中的一个连接到第二互连; 以及第二晶体管，其包括栅极结构，第二源极和第二漏极，所述第二源极和第二漏极中的一个连接到第三互连，并且所述第二源极和第二漏极中的另一个连接到第四互连。栅极结构包括栅极绝缘膜，栅极电极和设置在栅极绝缘膜和栅电极之间以调节阈值电压的阈值调制膜，第一晶体管的第一源极和第一漏极中的另一个被连接到栅电极。

4. 发明申请

US20130307054A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20130307054A1
公开(公告)日：2013-11-21
申请号：US13606292
申请日：2012-09-07
申请人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda , Atsuhiro Kinoshita , Daisuke Hagishima , Yoshifumi Nishi , Takahiro Kurita , Shinobu Fujita
发明人： Shinichi YASUDA , Kosuke Tatsumura , Mari Matsumoto , Koichiro Zaitsu , Masato Oda , Atsuhiro Kinoshita , Daisuke Hagishima , Yoshifumi Nishi , Takahiro Kurita , Shinobu Fujita
IPC分类号： H01L27/105
CPC分类号： G11C16/10 , H01L21/823456 , H01L21/823462 , H01L27/11526 , H01L27/11573 , H01L29/7881 , H01L29/792
摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.
摘要翻译：一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

5. 发明授权

US08450208B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08450208B2
公开(公告)日：2013-05-28
申请号：US13081629
申请日：2011-04-07
申请人： Yoshifumi Nishi , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki
发明人： Yoshifumi Nishi , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki
IPC分类号： H01L21/283
CPC分类号： H01L21/28518 , H01L29/1608 , H01L29/41708 , H01L29/456 , H01L29/6606 , H01L29/66068 , H01L29/6609 , H01L29/66272 , H01L29/665 , H01L29/6659 , H01L29/66712 , H01L29/732 , H01L29/7833 , H01L29/861
摘要： In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.
摘要翻译：在根据示例性实施例的半导体器件制造方法中，在n型半导体上沉积含硫的含硫膜，在含硫膜上沉积含有第一金属的第一金属膜，进行热处理通过使n型半导体和含硫膜反应形成金属半导体化合物膜，并将硫引入到正在形成的n型半导体与金属半导体化合物膜之间的界面上。

6. 发明申请

US20120077341A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20120077341A1
公开(公告)日：2012-03-29
申请号：US13081629
申请日：2011-04-07
申请人： Yoshifumi Nishi , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki
发明人： Yoshifumi Nishi , Atsuhiro Kinoshita , Hirotaka Nishino , Masamichi Suzuki
IPC分类号： H01L21/283
CPC分类号： H01L21/28518 , H01L29/1608 , H01L29/41708 , H01L29/456 , H01L29/6606 , H01L29/66068 , H01L29/6609 , H01L29/66272 , H01L29/665 , H01L29/6659 , H01L29/66712 , H01L29/732 , H01L29/7833 , H01L29/861
摘要： In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed.
摘要翻译：在根据示例性实施例的半导体器件制造方法中，在n型半导体上沉积含硫的含硫膜，在含硫膜上沉积含有第一金属的第一金属膜，进行热处理通过使n型半导体和含硫膜反应形成金属半导体化合物膜，并将硫引入到正在形成的n型半导体和金属半导体化合物膜之间的界面上。

7. 发明授权

US09361408B2 Memory system including key-value store 有权
标题翻译：内存系统包括键值存储
公开(公告)号：US09361408B2
公开(公告)日：2016-06-07
申请号：US13569605
申请日：2012-08-08
申请人： Takao Marukame , Atsuhiro Kinoshita , Kosuke Tatsumura
发明人： Takao Marukame , Atsuhiro Kinoshita , Kosuke Tatsumura
IPC分类号： G06F17/30 , G06F12/02
CPC分类号： G06F17/30982 , G06F12/0246 , G06F17/30097 , G06F17/3012 , G06F2212/7201
摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.
摘要翻译：根据一个实施例，包括密钥值存储的密钥值存储器的存储器系统包括密钥值数据作为一对密钥和对应于该密钥的值，包括接口，存储器块，地址获取电路和控制器。接口接收数据写/读请求或基于键值存储的请求。存储块具有用于存储数据的数据区域和包含键值数据的元数据表。地址获取电路响应于键的输入而获取地址。控制器执行存储器块的数据写/读请求，并将获取的地址输出到存储块，并根据键值存储执行请求。控制器通过接口输出与该键对应的值。

8. 发明申请

US20130042060A1 MEMORY SYSTEM INCLUDING KEY-VALUE STORE 有权
公开(公告)号：US20130042060A1
公开(公告)日：2013-02-14
申请号：US13569605
申请日：2012-08-08
申请人： Takao MARUKAME , Atsuhiro Kinoshita , Kosuke Tatsumura
发明人： Takao MARUKAME , Atsuhiro Kinoshita , Kosuke Tatsumura
IPC分类号： G06F12/00
CPC分类号： G06F17/30982 , G06F12/0246 , G06F17/30097 , G06F17/3012 , G06F2212/7201
摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.

9. 发明授权

US08576601B2 Content addressable memory 失效
标题翻译：内容可寻址内存
公开(公告)号：US08576601B2
公开(公告)日：2013-11-05
申请号：US13403398
申请日：2012-02-23
申请人： Takao Marukame , Tomoaki Inokuchi , Hideyuki Sugiyama , Mizue Ishikawa , Yoshiaki Saito , Atsuhiro Kinoshita , Kosuke Tatsumura
发明人： Takao Marukame , Tomoaki Inokuchi , Hideyuki Sugiyama , Mizue Ishikawa , Yoshiaki Saito , Atsuhiro Kinoshita , Kosuke Tatsumura
IPC分类号： G11C15/02
CPC分类号： G11C15/02 , G11C11/161 , G11C15/046 , H01L27/228
摘要： One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.
摘要翻译：一个实施例提供一种内容可寻址存储器，包括：一对自旋MOSFET，其包括：第一自旋MOSFET，其磁化状态根据存储的数据设置; 以及第二自旋MOSFET，其磁化状态根据存储的数据设定，第二自旋MOSFET与第一自旋MOSFET并联连接; 第一布线，被配置为施加栅极电压，使得第一自旋MOSFET和第二自旋MOSFET中的任何一个根据搜索数据变为导电; 以及配置为向第一自旋MOSFET和第二自旋MOSFET两者施加电流的第二布线。

10. 发明授权

US09262500B2 Memory system including key-value store 有权
标题翻译：内存系统包括键值存储
公开(公告)号：US09262500B2
公开(公告)日：2016-02-16
申请号：US13569542
申请日：2012-08-08
申请人： Atsuhiro Kinoshita , Takao Marukame , Kosuke Tatsumura
发明人： Atsuhiro Kinoshita , Takao Marukame , Kosuke Tatsumura
IPC分类号： G06F17/30 , G06F12/02
CPC分类号： G06F17/30587 , G06F12/0292
摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory.
摘要翻译：根据一个实施例，包括包含键值数据作为一对键和与该键对应的值的键值存储器的存储器系统包括第一存储器，控制电路和第二存储器。第一存储器被配置为包含用于存储数据的数据区域和包含键值数据的表区域。控制电路被配置为通过寻址来执行对第一存储器的写入和读取，并且基于键值存储执行请求。第二存储器被配置为根据来自控制电路的指令存储键值数据。控制电路通过使用存储在第一存储器中的键值数据和存储在第二存储器中的键值数据来执行设置操作。

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