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1. 发明申请

US20130076550A1 ANALOG-TO-DIGITAL CONVERTER 失效
标题翻译：模拟数字转换器
公开(公告)号：US20130076550A1
公开(公告)日：2013-03-28
申请号：US13536085
申请日：2012-06-28
申请人： Takao MARUKAME , Tetsufumi Tanamoto , Atsuhiro Kinoshita , Tomoaki Inokuchi , Masamichi Suzuki , Yoshiaki Saito
发明人： Takao MARUKAME , Tetsufumi Tanamoto , Atsuhiro Kinoshita , Tomoaki Inokuchi , Masamichi Suzuki , Yoshiaki Saito
IPC分类号： H03M1/34
CPC分类号： H03M1/1061 , H01L27/22 , H01L43/08 , H03M1/365
摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.
摘要翻译：根据实施例，模数转换器包括电压产生单元和多个比较器。电压产生单元被配置为通过多个可变电阻器分压参考电压以产生多个比较电压。多个比较器中的每一个被配置为将多个比较电压中的任何一个与模拟输入电压进行比较，并且基于比较电压和模拟输入电压之间的比较结果输出数字信号。多个可变电阻器中的每一个包括串联连接的多个可变电阻元件，并且多个可变电阻元件中的每一个具有根据外部信号可变地设置的电阻值。

2. 发明授权

US08405443B2 Pass transistor circuit with memory function, and switching box circuit including the pass transistor circuit 有权
标题翻译：具有存储功能的晶体管电路，以及包括传输晶体管电路的开关盒电路
公开(公告)号：US08405443B2
公开(公告)日：2013-03-26
申请号：US13419555
申请日：2012-03-14
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K17/687
CPC分类号： H01L27/112 , H03K19/17736
摘要： A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.
摘要翻译：根据实施例的传输晶体管电路包括：连接到第一信号线的第一输入/输出端子; 连接到第二信号线的第二输入/输出端子; 第一装置，具有连接到第一电源和第二端子的第一端子; 第二装置，具有连接到第二端子的第三端子和连接到第二电源的第四端子; 第一晶体管，其源极/漏极中的一个连接到第二端子，栅极接收第一控制信号; 以及第二晶体管，其栅极连接到第一晶体管的源极/漏极中的另一个，栅极/漏极中的一个连接到第一输入/输出端子，另一个源极/漏极连接到第二输入/输出端终奌站。第一和第二器件中的一个是非易失性存储器件，第一和第二器件中的另一个是MOSFET。

3. 发明申请

US20120273856A1 TUNNELING MAGNETORESISTIVE EFFECT ELEMENT AND SPIN MOS FIELD-EFFECT 有权
标题翻译：隧道磁场效应元件和旋转MOS场效应晶体管
公开(公告)号：US20120273856A1
公开(公告)日：2012-11-01
申请号：US13533198
申请日：2012-06-26
申请人： Mizue ISHIKAWA , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
发明人： Mizue ISHIKAWA , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
IPC分类号： H01L29/82
CPC分类号： G11B5/3909 , B82Y10/00 , B82Y25/00 , G01R33/098 , G11B5/3906 , G11C11/161 , G11C11/1659 , H01F10/1936 , H01F10/3254 , H01F10/3295 , H01L27/228 , H01L29/66984 , H01L43/08 , H01L43/10
摘要： A magnetoresistive effect element includes a first ferromagnetic layer, Cr layer, Heusler alloy layer, barrier layer, and second ferromagnetic layer. The first ferromagnetic layer has the body-centered cubic lattice structure. The Cr layer is formed on the first ferromagnetic layer and has the body-centered cubic lattice structure. The Heusler alloy layer is formed on the Cr layer. The barrier layer is formed on the Heusler alloy layer. The second ferromagnetic layer is formed on the barrier layer.
摘要翻译：磁阻效应元件包括第一铁磁层，Cr层，Heusler合金层，阻挡层和第二铁磁层。第一铁磁层具有体心立方晶格结构。 Cr层形成在第一铁磁层上并具有体心立方晶格结构。 Heusler合金层形成在Cr层上。阻挡层形成在Heusler合金层上。第二铁磁层形成在阻挡层上。

4. 发明申请

US20120223762A1 PASS TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, AND SWITCHING BOX CIRCUIT INCLUDING THE PASS TRANSISTOR CIRCUIT 有权
标题翻译：具有存储器功能的通用晶体管电路，以及包括通过晶体管电路的开关盒电路
公开(公告)号：US20120223762A1
公开(公告)日：2012-09-06
申请号：US13419555
申请日：2012-03-14
申请人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
发明人： Hideyuki Sugiyama , Tetsufumi Tanamoto , Takao Marukame , Mizue Ishikawa , Tomoaki Inokuchi , Yoshiaki Saito
IPC分类号： H03K17/00
CPC分类号： H01L27/112 , H03K19/17736
摘要： A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.
摘要翻译：根据实施例的传输晶体管电路包括：连接到第一信号线的第一输入/输出端子; 连接到第二信号线的第二输入/输出端子; 第一装置，具有连接到第一电源和第二端子的第一端子; 第二装置，具有连接到第二端子的第三端子和连接到第二电源的第四端子; 第一晶体管，其源极/漏极中的一个连接到第二端子，栅极接收第一控制信号; 以及第二晶体管，其栅极连接到第一晶体管的源极/漏极中的另一个，栅极/漏极中的一个连接到第一输入/输出端子，另一个源极/漏极连接到第二输入/输出端终奌站。第一和第二器件中的一个是非易失性存储器件，第一和第二器件中的另一个是MOSFET。

5. 发明授权

US08139403B2 Spin memory and spin transistor 有权
标题翻译：旋转记忆和自旋晶体管
公开(公告)号：US08139403B2
公开(公告)日：2012-03-20
申请号：US12885833
申请日：2010-09-20
申请人： Tomoaki Inokuchi , Takao Marukame , Mizue Ishikawa , Hideyuki Sugiyama , Hisanori Aikawa , Masahiko Nakayama , Tatsuya Kishi , Hiroaki Yoda , Yoshiaki Saito
发明人： Tomoaki Inokuchi , Takao Marukame , Mizue Ishikawa , Hideyuki Sugiyama , Hisanori Aikawa , Masahiko Nakayama , Tatsuya Kishi , Hiroaki Yoda , Yoshiaki Saito
IPC分类号： G11C11/15 , G11C29/82
CPC分类号： H01L29/66984 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1677 , G11C11/1697 , H01L27/224 , H01L43/08
摘要： Certain embodiments provide a spin memory including a memory cell including a ferromagnetic stacked film that has a stacked structure in which a first ferromagnetic layer, a first nonmagnetic layer, a second ferromagnetic layer, a second nonmagnetic layer, and a third ferromagnetic layer are stacked in this order or reverse order, the third ferromagnetic layer and the second ferromagnetic layer being antiferromagnetically exchange-coupled via the second nonmagnetic layer. The ferromagnetic stacked film includes a current path in which a first and second write currents flow from the first ferromagnetic layer to the third ferromagnetic layer to write a first and second magnetization states into the first ferromagnetic layer respectively, and the second write current is higher than the first write current.
摘要翻译：某些实施例提供一种自旋存储器，其包括一个存储单元，该存储单元包括一个具有层叠结构的铁磁层叠膜，其中第一铁磁层，第一非磁性层，第二铁磁层，第二非磁性层和第三铁磁层堆叠在其中该顺序或反向顺序，第三铁磁层和第二铁磁层经由第二非磁性层反铁磁交换耦合。铁磁层叠膜包括电流路径，其中第一和第二写入电流从第一铁磁层流向第三铁磁层，以将第一和第二磁化状态分别写入第一铁磁层，并且第二写入电流高于第一次写入电流。

6. 发明申请

US20110194342A1 NONVOLATILE MEMORY CIRCUIT USING SPIN MOS TRANSISTORS 有权
标题翻译：使用旋转MOS晶体管的非易失性存储器电路
公开(公告)号：US20110194342A1
公开(公告)日：2011-08-11
申请号：US12889881
申请日：2010-09-24
申请人： Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO
发明人： Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Takao MARUKAME , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO
IPC分类号： G11C11/14
CPC分类号： G11C14/0081
摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.
摘要翻译：某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

7. 发明授权

US07709867B2 Spin MOS field effect transistor and tunneling magnetoresistive effect element using stack having Heusler alloy 有权
公开(公告)号：US07709867B2
公开(公告)日：2010-05-04
申请号：US12194797
申请日：2008-08-20
申请人： Mizue Ishikawa , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
发明人： Mizue Ishikawa , Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： G11B5/3909 , B82Y10/00 , B82Y25/00 , G11B5/3929 , G11C11/161 , G11C11/1659 , H01L27/228 , H01L29/66984 , H01L43/08
摘要： A spin MOS field effect transistor includes a source electrode and a drain electrode each having a structure obtained by stacking an impurity diffusion layer, a (001)-oriented MgO layer and a Heusler alloy. The impurity diffusion layer is formed in a surface region of a semiconductor layer. The (001)-oriented MgO layer is formed on the impurity diffusion layer. The Heusler alloy is formed on the MgO layer.

8. 发明申请

US20100019798A1 SPIN MOSFET AND RECONFIGURABLE LOGIC CIRCUIT USING THE SPIN MOSFET 有权
标题翻译：旋转MOSFET和使用旋转MOSFET的可重新配置的逻辑电路
公开(公告)号：US20100019798A1
公开(公告)日：2010-01-28
申请号：US12486999
申请日：2009-06-18
申请人： Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi , Mizue Ishikawa , Takao Marukame
发明人： Yoshiaki Saito , Hideyuki Sugiyama , Tomoaki Inokuchi , Mizue Ishikawa , Takao Marukame
IPC分类号： H03K19/0944 , H01L29/00
CPC分类号： H01L29/66984 , B82Y25/00 , H01F10/3272 , H01F10/3286
摘要： It is made possible to provide a spin MOSFET that can minimize the increase in production costs and can perform both spin injection writing and reading. A spin MOSFET includes: a substrate that has a semiconductor region of a first conductivity type; first and second ferromagnetic stacked films that are formed at a distance from each other on the semiconductor region, and each have the same stacked structure comprising a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer stacked in this order, the second ferromagnetic stacked film having a film-plane area different from that of the first ferromagnetic stacked film; a gate insulating film that is formed on a portion of the semiconductor region, the portion being located between the first ferromagnetic stacked film and the second ferromagnetic stacked film; and a gate that is formed on the gate insulating film.
摘要翻译：可以提供一种可以使生产成本增加最小化的自旋MOSFET，并且可以执行自动注入写入和读取两种操作。自旋MOSFET包括：具有第一导电类型的半导体区域的衬底; 第一和第二铁磁层叠膜，其形成在半导体区域上彼此间隔一定距离处，并且各自具有包括依次层叠的第一铁磁层，非磁性层和第二铁磁层的相同层叠结构，第二铁磁体具有与第一铁磁性层叠膜不同的膜面积的层叠膜; 形成在所述半导体区域的一部分上的所述栅绝缘膜，所述栅极绝缘膜位于所述第一铁磁层叠膜和所述第二铁磁性堆叠膜之间; 以及形成在栅极绝缘膜上的栅极。

9. 发明申请

US20090244960A1 MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY 有权
标题翻译：磁电效应元件和磁记忆
公开(公告)号：US20090244960A1
公开(公告)日：2009-10-01
申请号：US12481726
申请日：2009-06-10
申请人： Yoshiaki SAITO , Hideyuki Sugiyama , Tomoaki Inokuchi
发明人： Yoshiaki SAITO , Hideyuki Sugiyama , Tomoaki Inokuchi
IPC分类号： G11C11/15
CPC分类号： G11C11/15 , H01F10/3254 , H01F10/3259 , H01F10/3263 , H01F10/3272 , H01L43/08
摘要： It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization direction is pinned, a magnetization free layer in which a magnetization direction is changeable, a tunnel barrier layer provided between the first magnetization pinned layer and the magnetization free layer, a non-magnetic metal layer provided on a first region in an opposite surface of the magnetization free layer from the tunnel barrier layer, a dielectric layer provided on a second region other than the first region in the opposite surface of the magnetization free layer from the tunnel barrier layer; and a second magnetization pinned layer provided to cover opposite surfaces of the non-magnetic metal layer and the dielectric layer from the magnetization free layer.
摘要翻译：可以提供高可靠性的磁阻效应元件和磁存储器，其以低功耗和电流写入操作，并且不会损坏元件。磁阻效应元件包括包含至少一个磁性层并且其中磁化方向被钉扎的第一磁化固定层，其中磁化方向可变的磁化自由层，设置在第一磁化固定层和第二磁化层之间的隧道势垒层磁化自由层，非磁性金属层，设置在磁化自由层的与隧道势垒层相反的表面的第一区域上，介电层设置在第二区域之外，该第二区域与磁化相反的表面中的第一区域自由层从隧道势垒层; 以及第二磁化固定层，其设置成覆盖非磁性金属层和电介质层与磁化自由层的相对表面。

10. 发明申请

US20090179667A1 RECONFIGURABLE LOGIC CIRCUIT 有权
标题翻译：可重新配置的逻辑电路
公开(公告)号：US20090179667A1
公开(公告)日：2009-07-16
申请号：US12339638
申请日：2008-12-19
申请人： Hideyuki SUGIYAMA , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO , Tetsufumi TANAMOTO
发明人： Hideyuki SUGIYAMA , Mizue ISHIKAWA , Tomoaki INOKUCHI , Yoshiaki SAITO , Tetsufumi TANAMOTO
IPC分类号： H03K19/094 , H03K19/173
CPC分类号： H03K19/1733 , G11C11/161 , G11C11/1675 , G11C11/1697
摘要： It is made possible to provide a reconfigurable logic circuit with which high integration can be achieved. A reconfigurable logic circuit includes: a multiplexer which includes a plurality of spin MOSFETs each having a source and drain containing a magnetic material, and a selecting portion including a plurality of MOSFETs and selecting a spin MOSFET from the plurality of spin MOSFETs, based on control data transmitted from control lines; a determining circuit which determines whether magnetization of the magnetic material of the source and drain of a selected spin MOSFET, which is selected by the selecting portion, is in a first state or in a second state; and a first and second write circuits which put the magnetization of the magnetic material of the source and drain of the selected spin MOSFET into the second and first states respectively by supplying a write current flowing between the source and drain of the selected spin MOSFET.
摘要翻译：可以提供可实现高集成度的可重构逻辑电路。可重配置逻辑电路包括：多路复用器，其包括多个自旋MOSFET，每个具有包含磁性材料的源极和漏极，以及包括多个MOSFET的选择部分，并且基于控制从多个自旋MOSFET中选择自旋MOSFET 从控制线传输的数据; 确定电路，其确定由选择部分选择的所选择的自旋MOSFET的源极和漏极的磁性材料的磁化是处于第一状态还是处于第二状态; 以及第一和第二写入电路，其通过提供在选定的自旋MOSFET的源极和漏极之间流动的写入电流，将所选自旋MOSFET的源极和漏极的磁性材料的磁化分别置于第二和第一状态。

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