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1. 发明授权

US09349797B2 SiC devices with high blocking voltage terminated by a negative bevel 有权
标题翻译：具有高阻断电压的SiC器件由负斜角端接
公开(公告)号：US09349797B2
公开(公告)日：2016-05-24
申请号：US13366658
申请日：2012-02-06
申请人： Lin Cheng , Anant K. Agarwal , Michael John O'Loughlin , Albert Augustus Burk, Jr. , John Williams Palmour
发明人： Lin Cheng , Anant K. Agarwal , Michael John O'Loughlin , Albert Augustus Burk, Jr. , John Williams Palmour
IPC分类号： H01L29/06 , H01L29/10 , H01L29/36 , H01L29/732 , H01L29/739 , H01L29/74 , H01L29/745 , H01L29/78 , H01L29/861 , H01L29/16
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0661 , H01L29/1004 , H01L29/1016 , H01L29/1095 , H01L29/1608 , H01L29/36 , H01L29/732 , H01L29/7397 , H01L29/74 , H01L29/745 , H01L29/861
摘要： The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (mΩ·cm2) and even more preferably less than 5 mΩ·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 mΩ·cm2 and even more preferably less than 7 mΩ·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 mΩ·cm2 and even more preferably less than 10 mΩ·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.
摘要翻译：本发明涉及具有高阻断电压和低导通电阻的碳化硅（SiC）半导体器件。在一个实施例中，半导体器件具有至少10千伏（kV）的阻断电压和小于10毫欧平方厘米（mΩ·cm 2·cm 2）的导通电阻，甚至更优选小于5mΩ 。在另一个实施例中，半导体器件具有至少15kV的阻断电压和小于15mΩ/ cm 2，甚至更优选小于7mΩ的导通电阻。在另一个实施例中，半导体器件具有至少20kV的阻断电压和小于20mΩ的导通电阻，并且甚至更优选地小于10mΩ·cm 2。半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT）或PIN二极管。

2. 发明申请

US20130026493A1 SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL 有权
标题翻译：具有高阻塞电压的SIC器件由负极水平端接
公开(公告)号：US20130026493A1
公开(公告)日：2013-01-31
申请号：US13366658
申请日：2012-02-06
申请人： Lin Cheng , Anant K. Agarwal , Michael John O'Loughlin , Albert Augustus Burk, JR. , John Williams Palmour
发明人： Lin Cheng , Anant K. Agarwal , Michael John O'Loughlin , Albert Augustus Burk, JR. , John Williams Palmour
IPC分类号： H01L29/24
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0661 , H01L29/1004 , H01L29/1016 , H01L29/1095 , H01L29/1608 , H01L29/36 , H01L29/732 , H01L29/7397 , H01L29/74 , H01L29/745 , H01L29/861
摘要： The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (mΩ·cm2) and even more preferably less than 5 mΩ·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 mΩ·cm2 and even more preferably less than 7 mΩ·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 mΩ·cm2 and even more preferably less than 10 mΩ·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.
摘要翻译：本发明涉及具有高阻断电压和低导通电阻的碳化硅（SiC）半导体器件。在一个实施例中，半导体器件具有至少10千伏（kV）的阻断电压和小于10毫欧平方厘米（mΩ·cm 2·cm 2）的导通电阻，甚至更优选小于5mΩ 。在另一个实施例中，半导体器件具有至少15kV的阻断电压和小于15mΩ/ cm 2，甚至更优选小于7mΩ的导通电阻。在另一个实施例中，半导体器件具有至少20kV的阻断电压和小于20mΩ的导通电阻，并且甚至更优选地小于10mΩ·cm 2。半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT）或PIN二极管。

3. 发明申请

US20130146894A1 BIPOLAR JUNCTION TRANSISTOR STRUCTURE FOR REDUCED CURRENT CROWDING 有权
标题翻译：用于减少电流冲击的双极接头晶体管结构
公开(公告)号：US20130146894A1
公开(公告)日：2013-06-13
申请号：US13323297
申请日：2011-12-12
申请人： Lin Cheng , Anant K. Agarwal , Sei-Hyung Ryu
发明人： Lin Cheng , Anant K. Agarwal , Sei-Hyung Ryu
IPC分类号： H01L29/73 , H01L21/331 , H01L29/24
CPC分类号： H01L29/0688 , H01L29/1004 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/66272 , H01L29/732
摘要： The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.
摘要翻译：本公开涉及一种双极结型晶体管（BJT）结构，其显着地减少了电流拥挤，同时改善了相对于传统BJT的电流增益。 BJT包括集电极，基极区和发射极。基极区形成在集电极上，并且包括至少一个非本征基极区域和在至少一个外部基极区域上方延伸以提供台面的本征基极区域。发射极形成在台面上。 BJT可以由诸如碳化硅（SiC）材料体系的各种材料体系形成。在一个实施例中，发射极形成在台面之上，使得基本上在外部基极区域上不形成发射极。通常但不一定，本征基区直接横向邻近于至少一个外在基区。

4. 发明申请

US20130264581A1 BIPOLAR JUNCTION TRANSISTOR WITH IMPROVED AVALANCHE CAPABILITY 有权
标题翻译：具有改进的AVALANCHE能力的双极连接晶体管
公开(公告)号：US20130264581A1
公开(公告)日：2013-10-10
申请号：US13438902
申请日：2012-04-04
申请人： Qingchun Zhang , Anant K. Agarwal , Lin Cheng
发明人： Qingchun Zhang , Anant K. Agarwal , Lin Cheng
IPC分类号： H01L29/73
CPC分类号： H01L29/7302 , H01L29/0626 , H01L29/1608 , H01L29/7424
摘要： A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs.
摘要翻译：公开了一种双极结型晶体管（BJT），其包括集电极层，集电极层上的基极层，基极层上的发射极层，以及埋设在集电极层中的凹陷区域。基极集电体平面位于基极层和集电极层之间。凹陷区域可以在底部 - 集电极平面之下。此外，凹部区域和基底层是第一种类型的半导体材料。通过将凹部嵌入集电极层中，凹陷区域和集电极层形成第一P-N结，其可以为BJT提供雪崩点。此外，集电极层和基极层形成第二P-N结。通过将雪崩点与第二P-N结分开，BJT可能会强烈地雪崩，从而降低雪崩诱发故障的可能性，特别是在碳化硅（SiC）BJT中。

5. 发明授权

US09601605B2 Bipolar junction transistor with improved avalanche capability 有权
公开(公告)号：US09601605B2
公开(公告)日：2017-03-21
申请号：US13438902
申请日：2012-04-04
申请人： Qingchun Zhang , Anant K. Agarwal , Lin Cheng
发明人： Qingchun Zhang , Anant K. Agarwal , Lin Cheng
IPC分类号： H01L29/73 , H01L29/06 , H01L29/74 , H01L29/16
CPC分类号： H01L29/7302 , H01L29/0626 , H01L29/1608 , H01L29/7424
摘要： A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs.

6. 发明授权

US09755018B2 Bipolar junction transistor structure for reduced current crowding 有权
公开(公告)号：US09755018B2
公开(公告)日：2017-09-05
申请号：US13323297
申请日：2011-12-12
申请人： Lin Cheng , Anant K. Agarwal , Sei-Hyung Ryu
发明人： Lin Cheng , Anant K. Agarwal , Sei-Hyung Ryu
IPC分类号： H01L29/06 , H01L29/66 , H01L29/732 , H01L29/10 , H01L29/16 , H01L29/20
CPC分类号： H01L29/0688 , H01L29/1004 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/66272 , H01L29/732
摘要： The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.

7. 发明授权

US09515135B2 Edge termination structures for silicon carbide devices 有权
标题翻译：碳化硅器件的边缘端接结构
公开(公告)号：US09515135B2
公开(公告)日：2016-12-06
申请号：US11331325
申请日：2006-01-12
申请人： Sei-Hyung Ryu , Anant K. Agarwal , Allan Ward
发明人： Sei-Hyung Ryu , Anant K. Agarwal , Allan Ward
IPC分类号： H01L31/0312 , H01L29/06 , H01L21/04 , H01L23/31 , H01L29/66 , H01L29/872 , H01L29/16
CPC分类号： H01L29/0619 , H01L21/0445 , H01L23/3192 , H01L29/0615 , H01L29/063 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/872 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An edge termination structure for a silicon carbide semiconductor device includes a plurality of spaced apart concentric floating guard rings in a silicon carbide layer that at least partially surround a silicon carbide-based junction, an insulating layer on the floating guard rings, and a silicon carbide surface charge compensation region between the floating guard rings and adjacent the surface of the silicon carbide layer. A silicon nitride layer is on the silicon carbide layer, and an organic protective layer is on the silicon nitride layer. An oxide layer may be between the silicon nitride layer and the surface of the silicon carbide layer. Methods of forming edge termination structures are also disclosed.
摘要翻译：用于碳化硅半导体器件的边缘终端结构包括在碳化硅层中的至少部分地围绕碳化硅基结的多个间隔开的同心浮动保护环，浮动保护环上的绝缘层和碳化硅浮动保护环之间的表面电荷补偿区域与碳化硅层表面相邻。氮化硅层位于碳化硅层上，有机保护层位于氮化硅层上。氧化物层可以在氮化硅层和碳化硅层的表面之间。还公开了形成边缘端接结构的方法。

8. 发明授权

US09478537B2 High-gain wide bandgap darlington transistors and related methods of fabrication 有权
标题翻译：高增益宽带隙达林顿晶体管及相关制造方法
公开(公告)号：US09478537B2
公开(公告)日：2016-10-25
申请号：US12503386
申请日：2009-07-15
申请人： Qingchun Zhang , Anant K. Agarwal
发明人： Qingchun Zhang , Anant K. Agarwal
IPC分类号： H01L29/24 , H01L29/73 , H01L21/331 , H01L27/082 , H01L21/82 , H01L29/16
CPC分类号： H01L27/0825 , H01L21/8213 , H01L29/1608 , H01L29/73
摘要： A packaged power electronic device includes a wide bandgap bipolar driver transistor having a base, a collector, and an emitter terminal, and a wide bandgap bipolar output transistor having a base, a collector, and an emitter terminal. The collector terminal of the output transistor is coupled to the collector terminal of the driver transistor, and the base terminal of the output transistor is coupled to the emitter terminal of the driver transistor to provide a Darlington pair. An area of the output transistor is at least 3 times greater than an area of the driver transistor in plan view. For example, an area ratio of the output transistor to the driver transistor may be between about 3:1 to about 5:1. Related devices and methods of fabrication are also discussed.
摘要翻译：封装的功率电子器件包括具有基极，集电极和发射极端子的宽带隙双极驱动晶体管，以及具有基极，集电极和发射极端子的宽带隙双极性输出晶体管。输出晶体管的集电极端子耦合到驱动晶体管的集电极端子，并且输出晶体管的基极端子耦合到驱动晶体管的发射极端子以提供达林顿对。在平面图中，输出晶体管的面积比驱动晶体管的面积至少大3倍。例如，输出晶体管与驱动晶体管的面积比可以在约3:1至约5:1之间。还讨论了相关装置和制造方法。

9. 发明申请

US20100289032A1 DIFFUSED JUNCTION TERMINATION STRUCTURES FOR SILICON CARBIDE DEVICES AND METHODS OF FABRICATING SILICON CARBIDE DEVICES INCORPORATING SAME 有权
标题翻译：用于硅碳化物装置的扩散结点终止结构和合成其中的碳化硅器件的制造方法
公开(公告)号：US20100289032A1
公开(公告)日：2010-11-18
申请号：US12719497
申请日：2010-03-08
申请人： Qingchun Zhang , Anant K. Agarwal , Tangali S. Sudarshan , Alexander Bolotnikov
发明人： Qingchun Zhang , Anant K. Agarwal , Tangali S. Sudarshan , Alexander Bolotnikov
IPC分类号： H01L29/24 , H01L21/225
CPC分类号： H01L29/1608 , H01L21/0465 , H01L21/223 , H01L29/0615 , H01L29/0657 , H01L29/0661 , H01L29/36 , H01L29/8613 , H01L29/872
摘要： An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×1014 cm−2.
摘要翻译：电子器件包括具有第一导电类型的碳化硅层和邻近碳化硅层的表面的主结，以及邻近主结的碳化硅层表面处的结终端区。连接终端区域中的电荷随着与主结的横向距离而减小，并且接合终端区域中的最大电荷可能小于约2×1014cm-2。

10. 发明申请

US20090004883A1 Methods of fabricating oxide layers on silicon carbide layers utilizing atomic oxygen 有权
标题翻译：使用原子氧在碳化硅层上制造氧化物层的方法
公开(公告)号：US20090004883A1
公开(公告)日：2009-01-01
申请号：US11229476
申请日：2005-09-16
申请人： Mrinal K. Das , Anant K. Agarwal , John W. Palmour , Dave Grider
发明人： Mrinal K. Das , Anant K. Agarwal , John W. Palmour , Dave Grider
IPC分类号： H01L21/316
CPC分类号： H01L21/049 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/3105 , H01L21/31658 , H01L21/32105 , Y10S438/931
摘要： Methods of forming oxide layers on silicon carbide layers are disclosed, including placing a silicon carbide layer in a chamber such as an oxidation furnace tube that is substantially free of metallic impurities, heating an atmosphere of the chamber to a temperature of about 500° C. to about 1300° C., introducing atomic oxygen in the chamber, and flowing the atomic oxygen over a surface of the silicon carbide layer to thereby form an oxide layer on the silicon carbide layer. In some embodiments, introducing atomic includes oxygen providing a source oxide in the chamber and flowing a mixture of nitrogen and oxygen gas over the source oxide. The source oxide may comprise aluminum oxide or another oxide such as manganese oxide. Some methods include forming an oxide layer on a silicon carbide layer and annealing the oxide layer in an atmosphere including atomic oxygen.
摘要翻译：公开了在碳化硅层上形成氧化物层的方法，包括将碳化硅层放置在基本上不含金属杂质的氧化炉管等室中，将室的气氛加热到约500℃的温度。至约1300℃，在室中引入原子氧，并将原子氧流过碳化硅层的表面，从而在碳化硅层上形成氧化物层。在一些实施方案中，引入原子包括在室中提供源氧化物的氧气，并使氮气和氧气的混合物流过源氧化物。源氧化物可以包括氧化铝或另一氧化物如氧化锰。一些方法包括在碳化硅层上形成氧化物层，并在包括原子氧的气氛中退火氧化物层。

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