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1. 发明申请

US20100293437A1 System to Improve Memory Failure Management and Associated Methods 失效
标题翻译：改善内存故障管理和相关方法的系统
公开(公告)号：US20100293437A1
公开(公告)日：2010-11-18
申请号：US12023498
申请日：2008-01-31
申请人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
发明人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/353 , H03M13/3707 , H03M13/6511
摘要： A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.
摘要翻译：改善存储器故障管理的系统可以包括存储器和用于确定存储器中的故障的错误控制解码器。系统还可以包括可以监视存储器中的故障的代理。该系统还可以包括一个表，其中错误控制解码器可以记录故障，以及代理可以在哪里读写。

2. 发明授权

US08352806B2 System to improve memory failure management and associated methods 失效
标题翻译：系统改善内存故障管理及相关方法
公开(公告)号：US08352806B2
公开(公告)日：2013-01-08
申请号：US12023498
申请日：2008-01-31
申请人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
发明人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/353 , H03M13/3707 , H03M13/6511
摘要： A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.
摘要翻译：改善存储器故障管理的系统可以包括存储器和用于确定存储器中的故障的错误控制解码器。系统还可以包括可以监视存储器中的故障的代理。该系统还可以包括一个表，其中错误控制解码器可以记录故障，以及代理可以在哪里读写。

3. 发明申请

US20110320911A1 Computer System and Method of Protection for the System's Marking Store 失效
标题翻译：计算机系统和系统标记商店的保护方法
公开(公告)号：US20110320911A1
公开(公告)日：2011-12-29
申请号：US12825521
申请日：2010-06-29
申请人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
IPC分类号： H03M13/09
CPC分类号： G06F11/1048
摘要： A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.
摘要翻译：一种用于控制在具有多个核心处理器和eDRAM缓存和互连总线的中央电子复合体中将标记存储更新的方法和装置，用于将服务处理器用于使用内部标记存储器将存储器控制器固件加载到双通道DDR3存储器控制器。存储器控制器的加载固件负责使用ECC解码器控制来跟踪ECC错误，由此所述标记存储器由慢ECC解码器写入，并且由快速ECC解码器读取，用于所述存储器控制器的每次读取操作，以提供阻塞机制用于在更新标记存储时通知标记存储固件，并确保标记存储固件无法写入标记存储，直到标记存储固件看到更新，而不会导致标记存储硬件超时。

4. 发明授权

US08650437B2 Computer system and method of protection for the system's marking store 失效
标题翻译：计算机系统和系统标记存储的保护方法
公开(公告)号：US08650437B2
公开(公告)日：2014-02-11
申请号：US12825521
申请日：2010-06-29
申请人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/1048
摘要： A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.
摘要翻译：一种用于控制在具有多个核心处理器和eDRAM缓存和互连总线的中央电子复合体中将标记存储更新的方法和装置，用于将服务处理器用于使用内部标记存储器将存储器控制器固件加载到双通道DDR3存储器控制器。存储器控制器的加载固件负责使用ECC解码器控制来跟踪ECC错误，由此所述标记存储器由慢ECC解码器写入，并且由快速ECC解码器读取，用于所述存储器控制器的每次读取操作，以提供阻塞机制用于在更新标记存储时通知标记存储固件，并确保标记存储固件无法写入标记存储，直到标记存储固件看到更新，而不会导致标记存储硬件超时。

5. 发明申请

US20110029807A1 IMPLEMENTING ENHANCED MEMORY RELIABILITY USING MEMORY SCRUB OPERATIONS 有权
标题翻译：使用存储器SCRUB操作实现增强的存储器可靠性
公开(公告)号：US20110029807A1
公开(公告)日：2011-02-03
申请号：US12510311
申请日：2009-07-28
申请人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
IPC分类号： G11C29/08 , G06F11/14 , G06F11/26
CPC分类号： G06F11/106
摘要： A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.
摘要翻译：一种用于使用存储器擦除操作来实现增强的存储器可靠性以确定间歇可校正错误的频率的方法和电路，以及提供了所述主题电路所在的设计结构。间歇性的内存擦除在移动到下一个内存擦除地址之前执行至少两次读取。跟踪识别出间歇性错误的多个间歇性错误，响应于识别一个失败的读取和一次读取至少两个读取。

6. 发明授权

US08103900B2 Implementing enhanced memory reliability using memory scrub operations 有权
标题翻译：使用内存清理操作实现增强的内存可靠性
公开(公告)号：US08103900B2
公开(公告)日：2012-01-24
申请号：US12510311
申请日：2009-07-28
申请人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
发明人： Richard E. Fry , Marc A. Gollub , Eric E. Retter , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： G06F11/106
摘要： A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.
摘要翻译：一种用于使用存储器擦除操作来实现增强的存储器可靠性以确定间歇可校正错误的频率的方法和电路，以及提供了所述主题电路所在的设计结构。间歇性的内存擦除在移动到下一个内存擦除地址之前执行至少两次读取。跟踪识别出间歇性错误的多个间歇性错误，响应于识别一个失败的读取和一次读取至少两个读取。

7. 发明授权

US08689080B2 Preemptive memory repair based on multi-symbol, multi-scrub cycle analysis 失效
标题翻译：基于多符号，多擦洗循环分析的抢占式内存修复
公开(公告)号：US08689080B2
公开(公告)日：2014-04-01
申请号：US13590998
申请日：2012-08-21
申请人： Jay W. Carman , Marc A. Gollub , Anshuman Khandual , Jyotindra Patel
发明人： Jay W. Carman , Marc A. Gollub , Anshuman Khandual , Jyotindra Patel
IPC分类号： G11C29/00
CPC分类号： G06F11/106
摘要： In some example embodiments, a method includes performing a memory scrub of a memory across a scrub cycle of multiple scrub cycles. The method includes identifying correctable errors of symbols in the memory that are a result of accesses from a section of the memory in response to the memory scrub. The method also includes performing an analysis across the multiple scrub cycles, wherein the performing of the analysis comprises determining whether at least two symbols across the multiple scrub cycles have at least one correctable error. The method includes responsive to determining that at least two symbols across the multiple scrub cycles have at least one correctable error, executing at least one repair of the memory that includes the section of memory.
摘要翻译：在一些示例性实施例中，一种方法包括在多个擦洗周期的擦洗循环之间执行存储器擦除。该方法包括识别作为响应于存储器擦除的来自存储器的一部分的访问的结果的存储器中的符号的可校正错误。该方法还包括在多个擦洗周期之间执行分析，其中分析的执行包括确定跨多个擦洗周期的至少两个符号是否具有至少一个可校正误差。该方法包括响应于确定跨多个擦洗周期的至少两个符号具有至少一个可校正错误，执行包括存储器部分的存储器的至少一次修复。

8. 发明申请

US20130007541A1 PREEMPTIVE MEMORY REPAIR BASED ON MULTI-SYMBOL, MULTI-SCRUB CYCLE ANALYSIS 有权
标题翻译：基于多符号的多播缓存循环分析进行的内存修复
公开(公告)号：US20130007541A1
公开(公告)日：2013-01-03
申请号：US13171675
申请日：2011-06-29
申请人： Jay W. Carman , Marc A. Gollub , Anshuman Khandual , Jyotindra Patel
发明人： Jay W. Carman , Marc A. Gollub , Anshuman Khandual , Jyotindra Patel
IPC分类号： H03M13/05 , G11C29/52 , G06F11/10
CPC分类号： G06F11/106
摘要： An apparatus includes a processor, a memory, and an error module operable on the processor. The error module is configured to perform a memory scrub of the memory across a scrub cycle of multiple scrub cycles. The error module is configured to identify correctable errors of symbols in the memory that are a result of accesses from a section of the memory in response to the memory scrub. The error module is configured to perform an analysis across the multiple scrub cycles, wherein the analysis comprises a determination whether at least two symbols across the multiple scrub cycles have at least one correctable error. The error module is configured to responsive to a determination that at least two symbols across the multiple scrub cycles have at least one correctable error, execute at least one repair of the memory that includes the section of memory.
摘要翻译：一种装置包括处理器，存储器和可在该处理器上操作的错误模块。错误模块被配置为在多个擦洗循环的擦洗循环中执行存储器擦除。错误模块被配置为识别存储器中的符号的可校正错误，其是响应于存储器擦除从存储器的一部分访问的结果。错误模块被配置为在多个擦洗周期之间执行分析，其中分析包括确定跨多个擦洗周期的至少两个符号是否具有至少一个可校正误差。错误模块被配置为响应于确定跨多个擦洗周期的至少两个符号具有至少一个可校正错误，执行包括存储器部分的存储器的至少一次修复。

9. 发明授权

US07895477B2 Resilience to memory errors with firmware assistance 失效
标题翻译：通过固件帮助恢复内存错误
公开(公告)号：US07895477B2
公开(公告)日：2011-02-22
申请号：US12132135
申请日：2008-06-03
申请人： Marc A. Gollub , Zane C. Shelley , Alwood P. Williams, III
发明人： Marc A. Gollub , Zane C. Shelley , Alwood P. Williams, III
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0712 , G06F11/0715 , G06F11/073
摘要： Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.
摘要翻译：本发明的实施例提供了一种中断处理器，其被配置为区分关键和非关键不可恢复的存储器错误，为每个存储器错误产生不同的动作。这样做可能允许系统从某些内存错误中恢复，而不必终止正在运行的进程。此外，当操作系统关键任务遇到不可恢复的错误时，这样的任务可以代表非关键过程（例如，当交换出虚拟存储器页面时）起作用。当这种情况发生时，中断处理程序可以响应存储器错误，具有相同的响应，这将导致进程本身执行存储器操作。此外，固件可以被配置为执行诊断以识别潜在的存储器错误并且在发生存储器区域状态改变之前警告操作系统，使得存储器错误将变得至关重要。

10. 发明申请

US20090300434A1 Clearing Interrupts Raised While Performing Operating System Critical Tasks 失效
标题翻译：在执行操作系统关键任务时清除中断
公开(公告)号：US20090300434A1
公开(公告)日：2009-12-03
申请号：US12132124
申请日：2008-06-03
申请人： Marc A. Gollub , Zane C. Shelley , Alwood P. Williams, III
发明人： Marc A. Gollub , Zane C. Shelley , Alwood P. Williams, III
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0712 , G06F11/0715 , G06F11/073
摘要： Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.
摘要翻译：本发明的实施例提供了一种中断处理器，其被配置为区分关键和非关键不可恢复的存储器错误，为每个存储器错误产生不同的动作。这样做可能允许系统从某些内存错误中恢复，而不必终止正在运行的进程。此外，当操作系统关键任务遇到不可恢复的错误时，这样的任务可以代表非关键过程（例如，当交换出虚拟存储器页面时）起作用。当这种情况发生时，中断处理程序可以响应存储器错误，具有相同的响应，这将导致进程本身执行存储器操作。此外，固件可以被配置为执行诊断以识别潜在的存储器错误并且在发生存储器区域状态改变之前警告操作系统，使得存储器错误将变得至关重要。

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