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1. 发明申请

US20180159556A1 ECC DECODER WITH MULTIPLE DECODING MODES 审中-公开
公开(公告)号：US20180159556A1
公开(公告)日：2018-06-07
申请号：US15613898
申请日：2017-06-05
申请人： WESTERN DIGITAL TECHNOLOGIES, INC.
发明人： Yan Dumchin , Yuri Ryabinin
IPC分类号： H03M13/25 , H03M13/11
CPC分类号： H03M13/255 , H03M13/1108 , H03M13/1137 , H03M13/116 , H03M13/1168 , H03M13/2778 , H03M13/3707 , H03M13/616 , H03M13/6508 , H03M13/6511
摘要： A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes multiple data processing units (DPUs) and a control circuit. The control circuit is responsive to a decoding mode indicator and to an error metric and is configured to configure the DPUs according to a decoding mode indicated by the decoding mode indicator. The control circuit is further configured to selectively set a reduced-power configuration of one or more components of the LDPC decoder at least partially based on the error metric.

2. 发明授权

US09189456B2 Technique for optimization and re-use of hardware in the implementation of instructions used in Viterbi and turbo decoding, using carry save arithmetic 有权
标题翻译：技术优化和重用硬件在执行指令中使用维特比和turbo解码，采用进位保存算术
公开(公告)号：US09189456B2
公开(公告)日：2015-11-17
申请号：US13916810
申请日：2013-06-13
申请人： Timothy D Anderson , Shriram D Moharil
发明人： Timothy D Anderson , Shriram D Moharil
IPC分类号： G06F7/50 , G06F17/12 , H03M13/39 , H03M13/41 , H03M13/00
CPC分类号： G06F17/12 , H03M13/3922 , H03M13/395 , H03M13/4107 , H03M13/6502 , H03M13/6511 , H03M13/6586
摘要： The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.
摘要翻译：本发明提供了一种用于在使用进位保存算术实现维特比和Turbo解码器中优化和重用硬件的手段。每个目标申请的成功规定要求面对两个主要问题。这些是：将求和项（a2-b2 + c2）与（x2 + y2 + z2）的计算合并; 和（a3 + b3-c3）与（x3 + y3 + z3）实现有效的计算方法（a4-b4-c4）; 并将该计算与（x4 + y4 + z4）合并。本发明解决了这两个问题，并且成功地将维特比指令与实现Turbo指令所需的硬件的完全重用相结合。通过有效地采用进位保存算法来优化两类指令所需的硬件。

3. 发明授权

US08938664B2 Error correction decoding by trial and error 有权
标题翻译：纠错解码通过反复试验
公开(公告)号：US08938664B2
公开(公告)日：2015-01-20
申请号：US13176758
申请日：2011-07-06
申请人： Idan Alrod , Eran Sharon , Simon Litsyn
发明人： Idan Alrod , Eran Sharon , Simon Litsyn
IPC分类号： H03M13/03 , H03M13/37 , H03M13/00
CPC分类号： H03M13/3738 , H03M13/3707 , H03M13/6502 , H03M13/6511
摘要： A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably, applying the first decoder consumes less power and is faster than applying the second decoder. Data are ported by encoding the data as a codeword, exporting the codeword to a corrupting medium, importing a representation of the codeword, and applying a first decoder to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword.
摘要翻译：通过将码字的第一解码器应用于码字的表示来解码码字的表示。如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。优选地，应用第一解码器消耗较少的功率并且比应用第二解码器更快。数据通过将数据编码为码字来移植，将码字导出到破坏性介质，导入码字的表示，以及将第一解码器应用于码字的表示。如果应用第一解码器不能解码码字的表示，则码字的第二解码器被应用于码字的表示。

4. 发明授权

US08938034B2 Processor for processing digital data with butterfly operator for the execution of an FFT/IFFT and telecommunication device 有权
标题翻译：用于使用蝶形运算符处理数字数据的处理器，用于执行FFT / IFFT和电信设备
公开(公告)号：US08938034B2
公开(公告)日：2015-01-20
申请号：US13511672
申请日：2010-11-29
申请人： Laurent Alaus , Dominique Noguet
发明人： Laurent Alaus , Dominique Noguet
IPC分类号： H04L27/06 , G06F17/14 , H03M13/39 , H03M13/41 , H03M13/00
CPC分类号： G06F17/142 , H03M13/3961 , H03M13/4107 , H03M13/6511
摘要： A processor for processing digital data includes at least one butterfly operator for executing an FFT/IFFT computation. This butterfly operator contains a first stage of complex multiplication and a second stage of complex addition and subtraction. Each of these two stages contains a plurality of addition/subtraction hardware modules and data transmission links between these modules. At least a part of the addition/subtraction modules of each stage of the butterfly operator and at least a part of the links between these modules are configurable with the aid of at least one programmable parameter, between a first configuration in which the butterfly operator carries out said fast Fourier transform computation and a second configuration in which the butterfly operator carries out a computation of branch metrics values and of path metrics and survivors values of a Viterbi algorithm.
摘要翻译：用于处理数字数据的处理器包括用于执行FFT / IFFT计算的至少一个蝶形运算符。该蝶形运算符包含复数乘法的第一阶段和复数加法和减法的第二阶段。这两个阶段中的每一个在这些模块之间包含多个加/减硬件模块和数据传输链路。蝶形运算符的每一级的至少一部分加/减模块和这些模块之间的至少一部分链路可以借助于至少一个可编程参数来配置，其中蝴蝶运算符携带的第一配置所述快速傅里叶变换计算和第二配置，其中蝶形运算符执行维特比算法的分支度量值以及路径量度和幸存者值的计算。

5. 发明授权

US08762813B2 Configurable coding system and method of multiple ECCS 有权
标题翻译：多种ECCS的可配置编码系统和方法
公开(公告)号：US08762813B2
公开(公告)日：2014-06-24
申请号：US12781744
申请日：2010-05-17
申请人： Yu-Shuen Tang , Chuang Cheng
发明人： Yu-Shuen Tang , Chuang Cheng
IPC分类号： G11C29/00
CPC分类号： H03M13/1105 , G06F11/10 , G06F11/1016 , H03M13/1102 , H03M13/152 , H03M13/353 , H03M13/3707 , H03M13/6511 , H03M13/6513 , H03M13/6516
摘要： A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes means for providing a selected parameter to the ECC codec for initializing the ECC codec. The parameter used for initializing the ECC codec is an error-free parameter.
摘要翻译：公开了一种用于存储器件或设备的多个纠错码（ECC）的可配置编码系统和方法。该系统包括ECC编解码器，其选择性地执行具有不同参数的不同错误校正。该系统还包括用于将ECC选择参数提供给ECC编解码器以便初始化ECC编解码器的装置。用于初始化ECC编解码器的参数是无错参数。

6. 发明授权

US08527850B1 Architecture and control of reed-solomon error identification and evaluation 有权
标题翻译：芦苇单体错误识别和评估的架构与控制
公开(公告)号：US08527850B1
公开(公告)日：2013-09-03
申请号：US13572783
申请日：2012-08-13
申请人： Ichiro Kikuchi , Siu-Hung Fred Au , Gregory Burd , Zining Wu , Jun Xu , Tony Yoon
发明人： Ichiro Kikuchi , Siu-Hung Fred Au , Gregory Burd , Zining Wu , Jun Xu , Tony Yoon
IPC分类号： H03M13/00
CPC分类号： H03M13/458 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/153 , H03M13/1545 , H03M13/1555 , H03M13/2906 , H03M13/3707 , H03M13/4146 , H03M13/45 , H03M13/451 , H03M13/63 , H03M13/6511
摘要： Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials.
摘要翻译：提供了系统和方法，用于实现里德 - 所罗门（RS）纠错码（ECC）系统的错误识别和评估。 BMA算法和/或列表解码可以产生与决策码字相关的一个或多个错误定位器多项式。加速Chien搜索可用于更快速地评估一个或多个错误定位器多项式。如果加速Chien搜索识别有效的错误定位器多项式，则可以使用正常的Chien搜索来识别错误位置，并且可以使用Forney的算法或等效技术来评估误差值。 RS ECC解码器可以包括评估错误定位器多项式或误差评估器多项式的计算电路。计算电路可以包括接收多项式的系数的计算组件。

7. 发明申请

US20130064323A1 Turbo Coding for Upstream and Downstream Transmission in Cable Systems 有权
标题翻译：用于电缆系统中上行和下行传输的Turbo编码
公开(公告)号：US20130064323A1
公开(公告)日：2013-03-14
申请号：US13613328
申请日：2012-09-13
申请人： Ravi Bhaskaran , Bruce J. Currivan , Thomas J. Kolze , Ba-Zhong Shen
发明人： Ravi Bhaskaran , Bruce J. Currivan , Thomas J. Kolze , Ba-Zhong Shen
IPC分类号： H04L27/04 , H04L27/06
CPC分类号： H04N21/437 , H03M13/29 , H03M13/2957 , H03M13/2966 , H03M13/6511 , H04L12/2801 , H04N7/17309
摘要： A method of transmitting data in a cable modem system includes the steps of encoding the data using forward error correction. The data is then encoded with Turbo encoding. The data is then sent to a modulation scheme. The data is then transmitted over a cable channel. The data is then demodulated. The data is then decoded using a Turbo decoder. An inverse of the forward error correction is then applied to the data.
摘要翻译：在电缆调制解调器系统中发送数据的方法包括使用前向纠错对数据进行编码的步骤。然后使用Turbo编码对数据进行编码。然后将数据发送到调制方案。然后通过有线信道传输数据。然后解调数据。然后使用Turbo解码器对数据进行解码。然后将前向纠错的逆向应用于数据。

8. 发明授权

US08219890B2 Denoising and error correction for finite input, general output channel 有权
标题翻译：有限输入，通用输出通道的去噪和纠错
公开(公告)号：US08219890B2
公开(公告)日：2012-07-10
申请号：US12246355
申请日：2008-10-06
申请人： Sergio Verdu , Tsachy Weissman , Erik Ordentlich , Gadiel Seroussi , Marcelo Weinberger
发明人： Sergio Verdu , Tsachy Weissman , Erik Ordentlich , Gadiel Seroussi , Marcelo Weinberger
IPC分类号： H03M13/00
CPC分类号： H03M13/3738 , H03M13/1102 , H03M13/1111 , H03M13/1515 , H03M13/2957 , H03M13/3746 , H03M13/45 , H03M13/612 , H03M13/6337 , H03M13/6511 , H03M13/6561 , H03M13/6577 , H03M13/6583 , H04L1/005
摘要： Systems and methods are disclosed for denoising for a finite input, general output channel. In one aspect, a system is provided for processing a noisy signal formed by a noise-introducing channel in response to an error correction coded input signal, the noisy signal having symbols of a general alphabet. The system comprises a denoiser and an error correction decoder. The denoiser generates reliability information corresponding to metasymbols in the noisy signal based on an estimate of the distribution of metasymbols in the input signal and upon symbol transition probabilities of symbols in the input signal being altered in a quantized signal. A portion of each metasymbol provides a context for a symbol of the metasymbol. The quantized signal includes symbols of a finite alphabet and is formed by quantizing the noisy signal. The error correction decoder performs error correction decoding on noisy signal using the reliability information generated by the denoiser.
摘要翻译：公开了用于对有限输入通用输出通道进行去噪的系统和方法。在一个方面，提供了一种用于响应于纠错编码的输入信号来处理由噪声引入信道形成的噪声信号的系统，该噪声信号具有一般字母的符号。该系统包括去噪器和纠错解码器。去噪器基于对输入信号中的符号符号的分布的估计，以及在量化信号中改变的输入信号中的符号的符号转换概率，在噪声信号中产生与元符号对应的可靠性信息。每个符号的一部分为符号的符号提供了一个上下文。量化信号包括有限字母表的符号，并且通过量化噪声信号形成。误差校正解码器使用由去噪器产生的可靠性信息对噪声信号进行纠错解码。

9. 发明授权

US08132082B2 Architecture and control of Reed-Solomon error-correction decoding 有权
公开(公告)号：US08132082B2
公开(公告)日：2012-03-06
申请号：US12249474
申请日：2008-10-10
申请人： Siu-Hung Fred Au , Gregory Burd , Zining Wu , Jun Xu , Ichiro Kikuchi , Tony Yoon
发明人： Siu-Hung Fred Au , Gregory Burd , Zining Wu , Jun Xu , Ichiro Kikuchi , Tony Yoon
IPC分类号： H03M13/00
CPC分类号： H03M13/458 , H03M13/098 , H03M13/1102 , H03M13/1515 , H03M13/153 , H03M13/1545 , H03M13/1555 , H03M13/2906 , H03M13/3707 , H03M13/4146 , H03M13/45 , H03M13/451 , H03M13/63 , H03M13/6511
摘要： Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

10. 发明授权

US08127214B2 Unified decoder for convolutional, turbo, and LDPC codes 有权
标题翻译：用于卷积，turbo和LDPC码的统一解码器
公开(公告)号：US08127214B2
公开(公告)日：2012-02-28
申请号：US11989448
申请日：2007-06-14
申请人： Alexey Trofimenko , Andrey Efimov , Andrey V Belogolovy , Vladislav A Chernyshev
发明人： Alexey Trofimenko , Andrey Efimov , Andrey V Belogolovy , Vladislav A Chernyshev
IPC分类号： H03M13/03
CPC分类号： H03M13/2957 , H03M13/1105 , H03M13/3905 , H03M13/3927 , H03M13/41 , H03M13/6511 , H03M13/6513 , H03M13/6583
摘要： A unified decoder is capable of decoding data encoded with convolutional codes, Turbo codes, and LDPC codes. In at least one embodiment, a unified decoder is implemented within a multi-standard wireless device.
摘要翻译：统一解码器能够解码用卷积码，Turbo码和LDPC码编码的数据。在至少一个实施例中，统一解码器在多标准无线设备内实现。

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