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1. 发明申请

US20090172498A1 Error correction in copy back memory operations 有权
标题翻译：复制内存操作中的错误更正
公开(公告)号：US20090172498A1
公开(公告)日：2009-07-02
申请号：US12005368
申请日：2007-12-27
申请人： Mark Shlick , Mark Murin , Menahem Lasser
发明人： Mark Shlick , Mark Murin , Menahem Lasser
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A method of storage and retrieval of data in a flash memory system, the flash memory system comprising a cache storage area of relatively high reliability, and a main storage area of relatively low reliability, the method comprising adding to data a level of error correction redundancy higher by a predetermined margin than that required for the cache storage area, writing the data to the cache storage area, and from the cache storage area copying the data directly to the main storage area, the predetermined margin being such as to allow subsequent error correction to compensate for errors accumulated from the cache storage area and the main storage area. In this way the memory die copy back operation can be used for copying the data from the cache to the main memory and two out of four transfers over the data bus to the flash controller are avoided.
摘要翻译：一种在闪速存储器系统中存储和检索数据的方法，所述闪速存储器系统包括相对较高可靠性的高速缓存存储区域和相对较低可靠性的主存储区域，所述方法包括向数据添加纠错冗余级别高于高速缓存存储区域所需的预定余量，将数据写入高速缓存存储区域，并从高速缓存存储区域将数据直接复制到主存储区域，预定余量允许后续纠错以补偿从高速缓存存储区域和主存储区域累积的错误。以这种方式，可以使用存储器管芯复制操作来将数据从高速缓存复制到主存储器，并且避免通过数据总线向闪存控制器传输四次。

2. 发明授权

US07613045B2 Operation sequence and commands for measuring threshold voltage distribution in memory 有权
标题翻译：用于测量存储器中阈值电压分布的操作顺序和命令
公开(公告)号：US07613045B2
公开(公告)日：2009-11-03
申请号：US11945120
申请日：2007-11-26
申请人： Mark Murin , Mark Shlick , Menahem Lasser , Cuong Trinh
发明人： Mark Murin , Mark Shlick , Menahem Lasser , Cuong Trinh
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C2211/5631 , G11C2211/5634
摘要： A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements.
摘要翻译：存储器件产生一个或多个读取参考电压，而不是明确地提供来自外部主机控制器的每个读取参考电压。该技术涉及向存储器件提供命令，其使得存储器件使用不同于先前读取中使用的参考电压的参考电压来读取一组存储元件，其中新的读取参考值不是明确的设置在存储设备外面。在一个实现中，存储器件被提供有初始参考电压和用于产生附加参考电压的步长。该技术可以用于例如确定一组存储元件的阈值电压分布。在这种情况下，可以对与该组存储元件相关联的字线施加电压扫描，并且可以基于导电存储元件的数量获得的数据。

3. 发明授权

US08443260B2 Error correction in copy back memory operations 有权
公开(公告)号：US08443260B2
公开(公告)日：2013-05-14
申请号：US12005368
申请日：2007-12-27
申请人： Mark Shlick , Mark Murin , Menahem Lasser
发明人： Mark Shlick , Mark Murin , Menahem Lasser
IPC分类号： G11C29/42 , G11C29/54
CPC分类号： G06F11/1064
摘要： A method of storage and retrieval of data in a flash memory system, the flash memory system comprising a cache storage area of relatively high reliability, and a main storage area of relatively low reliability, the method comprising adding to data a level of error correction redundancy higher by a predetermined margin than that required for the cache storage area, writing the data to the cache storage area, and from the cache storage area copying the data directly to the main storage area, the predetermined margin being such as to allow subsequent error correction to compensate for errors accumulated from the cache storage area and the main storage area. In this way the memory die copy back operation can be used for copying the data from the cache to the main memory and two out of four transfers over the data bus to the flash controller are avoided.

4. 发明申请

US20090135646A1 OPERATION SEQUENCE AND COMMANDS FOR MEASURING THRESHOLD VOLTAGE DISTRIBUTION IN MEMORY 有权
标题翻译：用于测量存储器中阈值电压分配的操作顺序和命令
公开(公告)号：US20090135646A1
公开(公告)日：2009-05-28
申请号：US11945120
申请日：2007-11-26
申请人： Mark Murin , Mark Shlick , Menahem Lasser , Cuong Trinh
发明人： Mark Murin , Mark Shlick , Menahem Lasser , Cuong Trinh
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C2211/5631 , G11C2211/5634
摘要： A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements.
摘要翻译：存储器件产生一个或多个读取参考电压，而不是明确地提供来自外部主机控制器的每个读取参考电压。该技术涉及向存储器件提供命令，其使得存储器件使用不同于先前读取中使用的参考电压的参考电压来读取一组存储元件，其中新的读取参考值不是明确的设置在存储设备外面。在一个实现中，存储器件被提供有初始参考电压和用于产生附加参考电压的步长。该技术可以用于例如确定一组存储元件的阈值电压分布。在这种情况下，可以对与该组存储元件相关联的字线施加电压扫描，并且可以基于导电存储元件的数量获得的数据。

5. 发明授权

US08650462B2 Probabilistic error correction in multi-bit-per-cell flash memory 失效
标题翻译：多比特单元闪存中的概率误差校正
公开(公告)号：US08650462B2
公开(公告)日：2014-02-11
申请号：US12401634
申请日：2009-03-11
申请人： Simon Litsyn , Idan Alrod , Eran Sharon , Mark Murin , Menahem Lasser
发明人： Simon Litsyn , Idan Alrod , Eran Sharon , Mark Murin , Menahem Lasser
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03M13/458 , G06F11/1012 , G06F11/1024 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C2029/0409 , H03M13/45
摘要： Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.
摘要翻译：根据系统或非系统ECC存储在多比特单元存储器的单元中的数据根据估计的概率被读取和校正（系统ECC）或恢复（非系统ECC）更多的读取位是错误的。在本发明的一种方法中，估计是先验的。在本发明的另一种方法中，估计仅基于包括读位的重要性或位页的读位的方面。在本发明的第三种方法中，估计仅基于读位的值。并不是所有的估计是相等的。

6. 发明授权

US08332574B2 Method for efficient storage of metadata in flash memory 有权
标题翻译：在闪存中有效存储元数据的方法
公开(公告)号：US08332574B2
公开(公告)日：2012-12-11
申请号：US12102063
申请日：2008-04-14
申请人： Menahem Lasser , Mark Murin
发明人： Menahem Lasser , Mark Murin
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7207
摘要： User data are stored in a memory that includes one or more blocks of pages by, for one of the blocks, and optionally for all of the blocks, whenever writing any of the user data to that block, writing the block according to a predefined plan for specifying, with respect to each page of that block, a portion of the user data that is to be written to that page. Alternatively or additionally, each page that stores user data has associated therewith a metadatum related to the age of the user data stored therein; and, for one of the blocks, at any time that two or more of the pages of that block store user data, a common value of the metadatum is associated with all such pages.
摘要翻译：每当将任何用户数据写入该块时，将用户数据存储在包括一个或多个块的块的存储器中，并且可选地针对所有块，并根据预定义的计划写入块用于针对该块的每个页面指定要写入该页面的用户数据的一部分。或者或另外，存储用户数据的每个页面与其相关联地存储与其中存储的用户数据的年龄有关的元数据; 并且对于其中一个块，在该块的两个或多个页面存储用户数据的任何时间，元数据的公共值与所有这些页面相关联。

7. 发明授权

US08069302B2 Flash memory storage system and method 有权
标题翻译：闪存存储系统和方法
公开(公告)号：US08069302B2
公开(公告)日：2011-11-29
申请号：US12830001
申请日：2010-07-02
申请人： Menahem Lasser , Mark Murin , Arik Eyal
发明人： Menahem Lasser , Mark Murin , Arik Eyal
IPC分类号： G06F13/14
CPC分类号： G11C11/5621 , G06F12/0246 , G06F12/0866 , G06F2212/2022 , G06F2212/7211 , G11C16/349 , G11C16/3495 , G11C2211/5641
摘要： A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells.
摘要翻译：闪速存储器存储系统包括包含多个存储器单元的存储器阵列和用于控制闪速存储器阵列的控制器。控制器专用于第一组存储器单元以每个单元的第一个位数和第二个单独的存储器单元组以每个单元的第二个位数来操作。提供了一种机制来将磨损均衡技术分别应用于两组细胞以均匀地磨损存储单元。

8. 发明申请

US20090268517A1 NON-VOLATILE MEMORY WITH ADAPTIVE SETTING OF STATE VOLTAGE LEVELS 有权
标题翻译：具有自适应状态电压水平的非易失性存储器
公开(公告)号：US20090268517A1
公开(公告)日：2009-10-29
申请号：US12111748
申请日：2008-04-29
申请人： Mark Murin , Menahem Lasser
发明人： Mark Murin , Menahem Lasser
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user.
摘要翻译：使用针对设备定制的电压和/或设备的部分（诸如非易失性存储元件的块或字线）访问非易失性存储器件。访问可以包括编程，验证或阅读。通过定制电压，可以优化性能，包括寻址由程序干扰引起的阈值电压变化。在一种方法中，存储器件中的不同存储元件组被编程为随机测试数据。确定不同组的存储元件的阈值电压分布。一组电压基于阈值电压分布来确定，并且存储在非易失性存储位置中，用于随后用于访问不同组的存储元件。可以在制造时确定该组电压以供随后在最终用户访问数据中使用。

9. 发明授权

US08990658B2 Probabilistic error correction in multi-bit-per-cell flash memory 有权
公开(公告)号：US08990658B2
公开(公告)日：2015-03-24
申请号：US12401630
申请日：2009-03-11
申请人： Simon Litsyn , Idan Alrod , Eran Sharon , Mark Murin , Menahem Lasser
发明人： Simon Litsyn , Idan Alrod , Eran Sharon , Mark Murin , Menahem Lasser
IPC分类号： H03M13/00 , G11C29/00 , H03M13/45 , G06F11/10 , G11C11/56 , G11C29/04
CPC分类号： H03M13/458 , G06F11/1012 , G06F11/1024 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C2029/0409 , H03M13/45
摘要： Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

10. 发明授权

US08103822B2 Method and apparatus for implementing a caching policy for non-volatile memory 有权
标题翻译：实现用于非易失性存储器的缓存策略的方法和装置
公开(公告)号：US08103822B2
公开(公告)日：2012-01-24
申请号：US12430089
申请日：2009-04-26
申请人： Amir Mosek , Menahem Lasser , Mark Murin
发明人： Amir Mosek , Menahem Lasser , Mark Murin
IPC分类号： G06G12/08
CPC分类号： G06F12/0804 , G06F12/0868 , G06F12/0888 , G06F2212/214
摘要： The present disclosure relates to methods, devices and computer-readable medium for implementing a caching policy and/or a cache flushing policy in a peripheral non-volatile storage device operatively coupled to a host device. In some embodiments, data is stored to a cache area of a non-volatile memory within the peripheral non-volatile storage device in accordance with a historical rate at which other data was received by the peripheral storage device from the host device and/or a historical average time interval between successive host write requests received and/or an assessed rate at which data is required to be written to the non-volatile memory and/or a detecting by the peripheral non-volatile memory device that the host has read the storage ready/busy flag. In some embodiments, data is copied from a cache storage area of the non-volatile memory to a main storage area in accordance with the historical rate and/or the historical average time interval.
摘要翻译：本公开涉及用于在可操作地耦合到主机设备的外围非易失性存储设备中实现高速缓存策略和/或缓存刷新策略的方法，设备和计算机可读介质。在一些实施例中，根据外围存储设备从主机设备接收其他数据的历史速率和/或一个或多个存储器，数据被存储到外围非易失性存储设备内的非易失性存储器的高速缓存区域接收的连续主机写入请求和/或需要将数据写入非易失性存储器的评估速率和/或由外围非易失性存储器设备检测到主机已读取存储器的历史平均时间间隔准备/忙碌标志在一些实施例中，根据历史速率和/或历史平均时间间隔将数据从非易失性存储器的高速缓存存储区域复制到主存储区域。

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